Imr Interrupt Mask Register - Samsung S3P80C5 User Manual

CONTROL REGISTERS
IMR
— Interrupt Mask Register
Bit Identifier
RESET Value RESET
Read/Write
Addressing Mode
.7
.6
.5
.4
.3–.2
.1
.0
NOTES:
1. When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
2. Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3P80C5/C80C5/C80C8 interrupt structure.
4-10
.7 .6
x x
R/W R/W
Register addressing mode only
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
1 Enable (un-mask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0 Disable (mask)
1 Enable (un-mask)
Not used for S3P80C5/C80C5/C80C8.
Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt
0 Disable (mask)
1 Enable (un-mask)
Not used for S3P80C5/C80C5/C80C8.
Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.5 .4
x x
R/W R/W R/W
S3P80C5/C80C5/C80C8
DDH
.3 .2 .1
x x x
R/W R/W
Set 1
.0
x
R/W