Samsung S3P80C5 User Manual page 69

CONTROL REGISTERS
CACON
— Counter A Control Register
Bit Identifier
RESET Value RESET
Read/Write
Addressing Mode
.7–.6
.5–.4
.3
.2
.1
.0
4-6
.7 .6
0 0
R/W R/W
Register addressing mode only
Counter A Input Clock Selection Bits
f
0 0
OSC
f /2
0 1
OSC
f /4
1 0
OSC
f /8
1 1
OSC
Counter A Interrupt Timing Selection Bits
0 0 Elapsed time for Low data value
0 1 Elapsed time for High data value
1 0 Elapsed time for combined Low and High data values
1 1 Invalid setting; not used for S3C80C5/C80C8.
Counter A Interrupt Enable Bit
0 Disable interrupt
1 Enable interrupt
Counter A Start Bit
0 Stop counter A
1 Start counter A
Counter A Mode Selection Bit
0 One-shot mode
1 Repeating mode
Counter A Output flip-flop Control Bit
0 Flip-flop Low level (T-FF = Low)
1 Flip-flop High level (T-FF = High)
.5 .4
0 0
R/W R/W R/W
S3P80C5/C80C5/C80C8
F3H
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W