Samsung S3P80C5 User Manual page 91

CONTROL REGISTERS
T1CON
— Timer 1 Control Register
Bit Identifier
RESET Value RESET
Read/Write
Addressing Mode
.7–.6
.5–.4
.3
.2
.1
.0
NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/
capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.
4-28
.7 .6
0 0
R/W R/W
Register addressing mode only
Timer 1 Input Clock Selection Bits
f /4
0 0
OSC
f /8
0 1
OSC
f /16
1 0
OSC
1 1 Internal clock (counter a flip-flop, T-FF)
Timer 1 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Overflow mode (OVF interrupt can occur)
1 0 Overflow mode (OVF interrupt can occur)
1 1 Overflow mode (OVF interrupt can occur)
Timer 1 Counter Clear Bit
0 No effect (when write)
1 Clear T1 counter, T1CNT (when write)
Timer 1 Overflow Interrupt Enable Bit
0 Disable T1 overflow interrupt
1 Enable T1 overflow interrupt
Timer 1 Match/Capture Interrupt Enable Bit
0 Disable T1 match interrupt
1 Enable T1 match interrupt
Timer 1 Match/Capture Interrupt Pending Flag
0 No T1 match interrupt pending (when read)
Clear T1 match interrupt pending condition (when write)
0
1 T1 match interrupt is pending (when read)
1 No effect (when write)
.5 .4
0 0
R/W R/W R/W
(note)
S3P80C5/C80C5/C80C8
FAH
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W