Samsung S3P80C5 User Manual page 204

S3P80C5/C80C5/C80C8
If Va voltage is under the 0.4 V
If Va voltage is over than 0.4 VDD, Reset pulse is not gernerated.
Voltage [V]
V
DD
SYSTEM RESET OPERATION
System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal
CPU and peripheral modules. This procedure brings the S3P80C5/C80C5/C80C8 into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level
for a minimum time interval after the power supply comes within tolerance. The minimum required reset
operation for a oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are
then reset to their default hardware values (see Tables 5-1).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0, 1 and 2 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.
— Peripheral control and data register settings are disabled and reset to their default hardware values (see
Table 5-1).
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed.
DD
(V
Figure 8-3. Timing Diagram for Power-on Reset Circuit
, Reset pulse signal is gernerated.
TV
DD
Rising Time)
DD
V
IH
Reset Pulse Width
RESET RESET
and POWER-DOWN
Va
= 0.85 V
DD
V = 0.4 V
IL DD
Reset pulse
V
DD
Time
8-3