Samsung S3P80C5 User Manual page 225

BASIC TIMER and TIMER 0
MSB
Timer 0 input clock selection bits:
00 = f /4096
OSC
01 = f /256
OSC
10 = f
OSC
11 = External clock (P2.1/T0CK)
Timer 0 operating mode selection bits:
00 = Interval mode
01 = Overflow mode (OVF interrupt can occur)
10 = Overflow mode (OVF interrupt can occur)
11 = PWM mode (OVF interrupt can occur)
10-4
Timer 0 Control Register (T0CON)
D2H, Set 1, R/W
.7 .6 .5
/8
Figure 10-2. Timer 0 Control Register (T0CON)
.4 .3 .2 .1
Timer 0 match interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending
Timer 0 match interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
S3P80C5/C80C5/C80C8
.0 LSB