Samsung S3P80C5 User Manual page 227

BASIC TIMER and TIMER 0
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at 'FFH', and then continues incrementing from '00H'.
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used
in PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference
data value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as
the data value is greater than ( > ) the counter value. One pulse width is equal to t
CLK
NOTE: Interrupts are usually not used when timer 0 is configurared to operate in PWM mode
10-6
Interrupt
Enable/Disable
(T0CON.1)
Counter
Comparator
Buffer Register
Data Register
Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode
IRQ0(T0INT)
PND (T0CON.0)
IRQ0 (T0OVF)
Match
CTL
T0CON.5
T0CON.4
Match Signal
T0CON.3
T0OVF
S3P80C5/C80C5/C80C8
× 256 (see Figure 11-4).
CLK
High level when
P2.0/ data > counter;
T0PWM Low level when
_
data < counter