Div Divide (Unsigned) - Samsung S3P80C5 User Manual

INSTRUCTION SET
DIV
— Divide (Unsigned)
DIV dst,src
Operation: dst ÷ src
dst (UPPER) ← REMAINDER
dst (LOWER) ← QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
the destination. When the quotient is ≥ 2
the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags: C: Set if the V flag is set and quotient is between 2
Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is ≥ 2
D: Unaffected.
H: Unaffected.
Format:
opc
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV
DIV
DIV
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains
the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the
destination register RR0 (R0) and the quotient in the lower half (R1).
6-38
8
or if divisor = "0"; cleared otherwise.
src dst
→
RR0,R2
→
RR0,@R2
→
RR0,#20H
8
, the numbers stored in the upper and lower halves of
8
and 2
Bytes
3
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
S3P80C5/C80C5/C80C8
9
–1; cleared otherwise.
Cycles Opcode
(Hex)
26/10 94
26/10 95
26/10 96
Addr Mode
dst src
RR R
RR IR
RR IM