Samsung S3P80C5 User Manual page 99

INTERRUPT STRUCTURE
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
The system-level control points in the interrupt structure are, therefore:
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
When writing the part of your application program that handles interrupt processing, be sure to include
the necessary register file address (register pointer) information.
EI
RESET
IRQ0, IRQ1,
IRQ4 and IRQ6- IRQ7
Interrupts
5-8
S Q
R
Interrupt Priority
Register
Figure 5-4. Interrupt Function Diagram
NOTE
Interrupt Request
Register (Read-only)
Interrupt Mask
Register
Global Interrupt Control
(EI, DI, or SYM.0
S3P80C5/C80C5/C80C8
Polling
Cycle
manipulation)
Vector
Interrupt
Cycle