Pld (Fpga) Version Up Method (Xilinx) [1] - Panasonic DVCPRO HD EX AJ-HD1200AP Service Manual

9-2-4. PLD (FPGA) Version up Method (XILINX) [1]

<SERVO CPLD IC>
A. Preparation
ITEM
C PLD WRITER
25pin-25pin Cable
Version Upgrade
Software
Version Upgrade Data
Personal Computer
B. Connection and Preparation
1. Connect the D-sub Cable between CN401 (for XILINX) connector of the CPLD WRITER (VFK1590) and
Personal Computer. (Refer to figure 9-2A-1 and table 9-2A-2)
2. Connect the CPLD WRITER Cable (VFK1590P4) between PLD version up connector on the relevant board
and P401 connector of CPLD WRITER. (Refer to figure 9-2A-1 and tables 9-2A-2, 9-2A-4)
3. Turn on the VTR and Personal Computer (Windows mode).
C. Boot up the Ver. Up Software and Ver. up Procedure
1.
Select "Start button" on the Windows Screenand then "Program" and then boot up the "Xilinx CPLD
Webpack" so that the menu appears as shown in figure 9-2D-2.
VFK1590
VFK1590P4 (VFK1590 standard)
Straight (Male - Female), Length : Within 1meter
XILINX WebPACK ISE Programmer (iMPACT) Software
Please download from the following URL
http://www.xilinx.com/support/download.htm
1. Open this page and then select "WebPACK ISE".
2. Before downloading, registration is required to get ID and Password.
3. After registration, click "Download ISE WebPACK" button.
4. Select "CUSTOM" in "Typical Download Configurations" menu.
5. Check "FPGA Prog."
6. Click Download button.
7. Follow the instruction of next page.
cdf File (Included in VVVSI4289A file).
(Copy all files of the VVVSI4289A which is included " *.cdf " file to floppy disk)
WINDOWS 95® or 98®
Table 9-2D-1
Figure 9-2D-2
INF-37
REMARK
in "Custom Design Configuration" page.