Udc (Aj-Ya120Ag) Block Diagram - Panasonic DVCPRO HD EX AJ-HD1200AP Service Manual

UDC (AJ-YA120AG) BLOCK DIAGRAM

(2)
(2)
FROM
VOUT_SYS
(2)
CIRCUIT
P150<3> P100<1>
UD_74M_CLK (2)
62A 62A UD_74M
IC213<2>
(19)
(2)
IC212<2>
(19)
P150<3> P100<1>
UD_27M_CLK (2)
66A 66A UD_27M
IC205<2>
(4) (16)
70B 70B UD_HD_CF
IC205<2>
(7) (13)
70A 70A UD_SD_CF
P150<3> P100<1> IC206,207<2>
(2-9,2) (11-18,18)
23A-27B 23A-27B ADDRESS (8:0)
P150<3> P100<1> IC208<2>
(2-9) (11-18)
28A-31B 28A-31B DATA (7:0)
P150<3> P100<1>
IC209<2>
SYS_WR_N
(3) (17)
33A 33A SYS_WE_N
P150<3> P100<1>
IC209<2>
SYS_RD_N
(2) (18)
33B 33B SYS_RE_N
P150<3> P100<1>
IC209<2>
UPDOWN_CS_N
(4) (16)
32A 32A F_CONV_CS
P150<3> P100<1>
IC209<2>
PW_RST_N
(5) (15)
32B 32B SYS_RST_L
P150<3> P100<1>
IC205<2>
(2) (18)
68B 68B UD_HD_H
P150<3> P100<1> IC205<2>
(5) (15)
68A 68A UD_SD_H
IC205<2>
P150<3> P100<1>
IN INREF FRM
(3) (17)
69B 69B UD_HD_FRM
P150<3> P100<1> IC205<2>
IN OUTREF FRM (6) (14)
69A 69A UD_SD_FRM
P150<3> P100<1>
IC205<2>
32_PULL
(8) (12)
71B 71B FILM_REF
(NOT USED)
IN CLK1
IC200<2>(2-9)
P150<3> P100<1> IC200<2>(12-19)
10 10
IC201<2>(2,3)
IC201<2>(18,19)
2B-11B 2B-11B DWN_YE(0)-(9)
IC202<2>(6-9)
P150<3> P100<1> DFF IC202<2>(12-15)
10 10
IC203<2>(2-7)
IC203<2>(14-19)
2A-11A 2A-11A DWN_PB(0)-(9)
IC200-IC204<2>
IN_HD
OUT_HD
27_PROC
74_PROC
IC214<2>
(16)
IC215<2>
(18)
PROCESS_CLK
IC211<2>
INCLK3
IC216<2>
(4) (16) INCLK1
(18)
IC216<2>
INCLK2
(3) (17)
IC210<2>
IC216<2>
(18) (9) (11) INCLK4
OUT_SD_N
IC217<2>
(17) (9) (11)
OUTCLK4
OUTCLK3
IC217<2>
(5) (15) OUTCLK2
IN_SD_N
(14)
IC340<3>
IC400<4>
TP340
9 151 IN CLK2
(231-239)
8
(219-226) 34 OUT CLK2
IP PROC
(215)
(216)
(217)
Resister Values
Serializer
(156)
TP343
<3>
(98) System Timing
TP345
<3>
(100)
TRS add
Y/C Mux for HD
TP404
(105)
(181) OUT_FR_RST
TP344
<3>
(99) TP405
(184)
(180) FILM_RST
TP346
<3>
(101)
TP365<3>
TP347
ASIC_Y (9:0)
195-198
<3>
10 (183-262)
(102) / SD 4:2:2 (9:0)
200-205
TP369<3>
182-187
ASIC_C (9:0) 10 (261-339)
189-192
TP200
CS(2:0)
RAS
CAS
WE
CLKEN
DATAEN
2-4
7-11
IN_Y_EVEN
13,16
IC500-503 IC504-507
61-66
IN_PB
68-71
Timing Control
(103) (104) (105) (213)
TP600<6>
ASIC needs TRS.
IC401<4>
(2) (18) ASIC_CLK
Buff
TP409<4>
IC600<6> (L6)
TP400<4> TP408<4> 1/2 Div.
TP602 TP601
/ throu.
(K17)
OUT_SD (W4)
IN_SD
(V3)
(N4)
IN_INREF_CF (F18)
IN_OUTREF_CF (G18)
158 181 546 234
C7,D7,E7,F7
C6,D6,E6
(259-337) ASIC_OUT_Y (9:0) C5,D5,E5
C8,D8,E8,F8
ASIC_OUT_PB (9:0) C9,D9,E9,F9
(364-413) PB (9:0) / C (9:0)
G9,C10
Y mux for HD
C14,D14,E14
F14,G14,C15
UFC1000
ASIC_OUT_PR (9:0)
D15,E15,F15
(442-520) PR (9:0)
G15
FIFO timing
ASIC
(444)
PROGRAM_CLK
(D11)
TRS detect
BGA
(445)
PROGRAM_RST_N
(E17)
TRS add
(131)
UFC_RST_N
(D17)
SETUP adjust
(443)
PROGRAM_DATA
(C17)
(105)
OUT_FR_RST_N
(C18)
(184)
FILM_RST
(D18)
(M4)
NCE_TX
RESERVE2 (T12)
RESERVE1 (R13)
4
RESERVE0 (T13)
4
4
4 IN INREF H (F20)
4
4
IN INREF FRM (F19)
15-19 2-13 21-26
37,39 40-53 34-39 (38)
IN OUTREF H (G20)
IC508-511 IC512-515<5>
IN OUTREF FRM (G19)
32 PULL (G17)
Output Control
TP700<7>
HALF_CLK
(V5)
Output signal does not have TRS.
TP701<7>
V6,W6,Y6
V7,W7,Y7 OUT Y_EVEN (9:0) IC702<7>(2-9)
IC702,703<7>
10
IC702<7>(12-19)
U8,V8,W8,Y8 / SD 4:2:2 (9:0) / Y(9:0) IC703<7>(2,3)
IC703<7>(18,19)
DFF
11
TP703<7>
T14,U14,V14,W14
Y14,U15,V15,W15 IC704<7>(6-9)
IC704,705<7>
10
Y15,U16 IC704<7>(12-14)
OUT PB (9:0) / C (9:0) IC705<7>(2-7)
IC705<7>(14-19)
DFF
11
IC700<7>
SUB_UD_CLK
(V12) UD_CLK (9) (11)
TP657<6>
OUT_FRM SUB_OUT_FRM
(V20) (3) (17)
TP659<6>
Buff
OUT_H
(Y20) (2) (18)
OUT_CF
(U20) (6) (14)
TO
VOUT_SYS
CIRCUIT
TP705<7>
P100<1> P150<3>
10
SUB_YE(0)-(9) 45B-54B 45B-54B
P100<1> P150<3>
10
SUB_PB(0)-(9) 35B-44B 35B-44B
P100<1> P150<3>
UD_CLK 57A 57A
P100<1> P150<3>
SUB_OUT_FRM 59B 59B
P100<1> P150<3>
SUB_OUT_H 59A 59A
P100<1> P150<3>
SUB_OUT_CF 60B 60B