Analog Devices AD9830 Instruction Manual page 9

Register Size
FREQ0 REG 32 Bits
FREQ1 REG 32 Bits
PHASE0 REG 12 Bits
PHASE1 REG 12 Bits
PHASE2 REG 12 Bits
PHASE3 REG 12 Bits
Figure 18. AD9830 Control Registers
REV. B
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
START 0Hz
RBW 1kHz
Figure 17. f = 50 MHz, f
MCLK
Word = 547AE148
Description
Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
STOP 25MHz
VBW 3kHz ST 50 SEC
= 16.5 MHz, Frequency
OUT
A2 A1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Figure 19. Addressing the Control Registers
D15
MSB
Figure 20. Frequency Register Bits
D15 D14 D13 D12 D11
X X X X
X = Don't Care
Figure 21. Phase Register Bits
–9–
AD9830
A0 Destination Register
0 FREQ0 REG 16 LSBs
1 FREQ0 REG 16 MSBs
0 FREQ1 REG 16 LSBs
1 FREQ1 REG 16 MSBs
0 PHASE0 REG
1 PHASE1 REG
0 PHASE2 REG
1 PHASE3 REG
MSB
D0
LSB
D0
LSB