Fpga Configuration; Reset Scheme; Power Management; Table 4-11 Fpga Configuration Controls - SMART Embedded Computing RTM-ATCA-F140 Series Installation & Use Manual

Functional Description
4.8.8

FPGA Configuration

The RTM FPGA configuration is loaded at power-up from one of two SPI flash devices. One
device is writable/upgradeable and the other is non writable/golden for recovery purposes.
The selection in which device is used is controlled by switch S1 position 1, according to the
following table.
Table 4-11
Switch Setting
S1.1 = Off
S1.1 = On
The configuration flash devices can be field upgraded using a SPI-controlled flash
programmer in the FPGA.
4.9

Reset Scheme

The front blade provides a single reset signal, RTM_RST#, over the Zone 3 connectors.
This signal is asserted when a master reset of the front blade occurs.
RTM_RST# directly resets the RTM FPGA. The BCM8727, BCM84754, BCM84740, and
QSFP+ slot are reset from a secondary reset generated by the RTM FPGA. This allows
software control of the PHY and QSFP+ resets in addition to hardware control via the
RTM_RST# signal. After the hardware reset, the PHYs and QSFP+ are held in reset until
released by software.
4.10

Power Management

The front blade provides two separate power supplies using the Zone 3 connectors:
+3.3V management power – one pin

+12V payload power – four pins

The maximum current draw, which is limited by the pin's current handling capability, is 0.8A
for the management power and 3.2A for the payload power.
The management power is used to directly power the devices connected to the front blade
2
I C bus, namely for serial EEPROM, temperature sensors and I/O extender device.
+12V payload power is the source for the on-board DC-to-DC converters needed for the
RTM payload.
70
FPGA Configuration Controls
RTM-ATCA-F140 Series Installation and Use (6806800M97M)
FPGA Flash
Writable Bank (default)
Non-writable (golden)
Functional Description