Gps Connectors; Fpga; Front Blade Interface - SMART Embedded Computing RTM-ATCA-F140 Series Installation & Use Manual

Table 4-10 BCM84740 PHY Addressing (continued)
PHY
Addr
High
Bits
4.7

GPS Connectors

The 1PPS, 10MHz, and TOD inputs for connection to an external GPS receiver are not
supported.
4.8

FPGA

The RTM-ATCA-F140 includes a Xilinx XC3S200A-4 FPGA that which performs the
following functions:
Access to control and status signals on SFP, SFP+, and QSFP+

Access to control and status signals on the BCM8727, BCM84754, and BCM84740

Reset handling

SPI flash programmer and multiplexing for BCM8727, BCM84754, and BCM84740

configuration
UART with selectable outputs for the optional GPS receiver (functionality not

initially implemented)
4.8.1

Front Blade Interface

The RTM-ATCA-F140 includes an SPI interface between the front blade service processor
and the RTM FPGA. There is also an active low interrupt line to the front blade to request
service.
RTM-ATCA-F140 Series Installation and Use (6806800M97M)
PHY
Addr
Channel Source
Low
Bits
1 Fabric b01
2 Fabric b10
3 Fabric b11
Functional Description
PHY Switch QSFP+
Addr Port Port
FIX_P14
1
Lane 1
FIX_P14
2
Lane 2
FIX_P14
3
Lane 3
Management
Channel
67