Functional Description
Table 4-9
Pin
18
19
4.6.6.1
QSFP+ I
The QSFP+ I
connected to the BCM84740 which includes a mechanism to allow access to the port
through the PHY management channel.
4.6.6.2
QSFP+ Status Signals
The QSFP+ status signals, MODPRS#, and INT#, are individually connected to the
BCM84740 which monitors them. The signals are also connected to the RTM FPGA to
allow fast detection of a loss of signal condition. Refer to
further details.
4.6.6.3
QSFP+ Control Signals
The QSFP+ LPMODE signal is connected to the BCM84740. This allows software control
of the power mode, or hardware control through deassertion of the TXONOFF signal.
4.6.7
PHY Management Interfaces
The BCM84740 provides a single MDC/MDIO management port to access all four channels
and allows bits 0 and 1 of the PHY address for each channel to be individually programmed,
with bits 2 - 4 being common. The next table shows the address allocation and
management port definition for each channel.
Table 4-10 BCM84740 PHY Addressing
PHY
Addr
High
Bits
b000
66
QSFP+ Connector Pin Assignment (continued)
Signal
RX1-
GND
2
C Bus
2
C bus signals (I2C_SDA and I2C_SCL) from each SFP+ site are individually
PHY
Addr
Channel Source
Low
Bits
0
Fabric
b00
RTM-ATCA-F140 Series Installation and Use (6806800M97M)
Pin
Signal
21
RX2-
20
GND
GPS Connectors on page 67
PHY
Switch
QSFP+
Addr
Port
Port
FIX_P14
Fabric
0
Lane 0
QSFP+
Functional Description
for
Management
Channel
FIX_XG_MDC2/
MDIO2
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