Bcm84754 Control And Status; Bcm84740 Control And Status; Reset Handling; Spi Flash - SMART Embedded Computing RTM-ATCA-F140 Series Installation & Use Manual

4.8.4

BCM84754 Control and Status

The RTM FPGA provides register access to the BCM84754 TXONOFF signals. This allows
the PHYs to be placed into low-power mode and disables the associated SFP+
transmitters. The RTM FGPA provides access to the LASI status signals of the
BCM84754s. Each signal can be programmed to cause an interrupt when its state
changes.
4.8.5

BCM84740 Control and Status

The RTM FPGA provides register access to the BCM84740 TXONOFF signal. This allows
the PHY to be placed into low-power mode and also drives LPMODE to the QSFP+ site.
According to the QSFP+ spec, assertion of LPMODE may or may not cause the transmitter
to be disabled. More detail can be found in section
RTM FGPA provides access to the LASI status signal of the BCM84740. This signal can be
programmed to cause an interrupt when its state changes.
4.8.6

Reset Handling

The RTM FPGA provides register control of the reset inputs to the BCM8727, BCM84754,
BCM84740, and the QSFP+ port. This allows the front blade control processor to reset the
PHYs and QSFP+. At system reset, as indicated by the Zone 3 RTM_RST# signal, the
PHYs and QSFP+ are forced into reset until this is cleared by a register write. This is to
ensure that the PHYs are in reset until the telecom clock subsystem has been programmed
if necessary to provide the PHY reference clocks.
4.8.7

SPI Flash

The SPI ports from the BCM8727, BCM84754, and BCM84740 connect to the FPGA along
with three SPI flash devices, one for each type. Register settings allow access to be
granted to any of the PHYs and also provide a programming port.
RTM-ATCA-F140 Series Installation and Use (6806800M97M)
Functional Description
Transmitter Control on page
64. The
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