Analog Interface; Digital Interface; Power Supplies; J1-Analog Interface Pinout - Texas Instruments MSOP-8EVM-PDK User Manual

Analog Interface

2 Analog Interface
For maximum flexibility, the modular MSOP-8EVM is designed for easy interfacing to multiple analog
sources. Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient,
10-pin, dual-row header/socket combination at J1. This header/socket provides access to the analog input
pins of the ADC. Consult Samtec at
mating connector options.
Pin Number
J1.2
J1.4
J1.6
J1.8
J1.10
J1.12
J1.14
J1.16
J1.18
J1.20
J1.15
J1.1 to J1.19
(odd)
3

Digital Interface

The modular MSOP-8EVM is designed for easy interfacing to multiple control platforms. Samtec part
numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient, 10-pin, dual-row
header/socket combination at J2. This header/socket provides access to the digital control and serial data
pins of the MSOP-8EVM. Consult Samtec at
mating connector options.
Pin Number
J2.1
J2.3
J2.5
J2.7
J2.9
J2.11
J2.13
J2.15
J2.17
J2.19
4

Power Supplies

The modular MSOP-8EVM board requires +5V dc for the analog section. This power source supplies the
voltage reference (U2), the reference buffer (U4), and optionally, the ADC installed on the EVM (via
JMP1). Supply voltages of +1.8V to +5V dc for the digital section are also required. When used in
combination with one of the DAP Interface boards, J3 provides connection to the common power bus
described in the 5-6 K Interface Board User's Guide, (SLAU104).
4
MSOP-8EVM and MSOP-8EVM-PDK
http://www.samtec.com
Table 2. J1—Analog Interface Pinout
Signal Description
AD_IN+ Noninverting input for differential devices, and analog input for single-ended devices
AD_IN– Inverting input for differential devices, and analog ground for single-ended devices
Unused
Unused
Unused
Pins are unused and should be left open for use with future amplifier and sensor input
modules
Unused
Unused
Unused
REF(–) Unused
REF(+) External reference source input
Unused Unused
AGND Analog ground connections (except J1.15)
Table 3. J2—Digital Interface Pinout
Signal Name Description
Chip select, active low signal. Enables data transfer, jumper configurable (see the
CS
schematic located at the end of this document)
SCLK Serial clock
SCLKr Serial clock return (for DSP host systems)
Frame sync for DSP host systems; alternate chip select through JMP2 (see the schematic
FS
located at the end of this document)
FSr Frame sync return (for DSP host systems)
Unused Unused
SDO Serial data output
Unused Unused
Unused Unused
SPARE
Copyright © 2008–2016, Texas Instruments Incorporated
or call 1-800-SAMTEC-9 for a variety of
http://www.samtec.com or 1-800-SAMTEC-9 for a variety of
Table 4
SBAU140A – December 2008 – Revised February 2016
www.ti.com
shows the pinout for J3.
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