Texas Instruments MSP430FR57 Series User Manual

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Msp430Fr57Xx Family User's Guide
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MSP430FR57xx Family

User's Guide

Literature Number: SLAU272C

May 2011 – Revised November 2013

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Page 1 MSP430FR57xx Family User's Guide Literature Number: SLAU272C May 2011 – Revised November 2013...
Page 2: Table Of Contents
1.15.3 SFRRPCR Register ......................1.16 SYS Registers ....................1.16.1 SYSCTL Register ..................... 1.16.2 SYSJMBC Register ..................... 1.16.3 SYSJMBI0 Register ..................... 1.16.4 SYSJMBI1 Register Contents SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 3 Constant Generator Registers (CG1 and CG2) ..............4.3.5 General-Purpose Registers (R4 to R15) ......................Addressing Modes ....................4.4.1 Register Mode ..................... 4.4.2 Indexed Mode SLAU272C – May 2011 – Revised November 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 4 ........................ DMA Controller ................Direct Memory Access (DMA) Introduction ......................DMA Operation ..................7.2.1 DMA Addressing Modes ................... 7.2.2 DMA Transfer Modes Contents SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 5 CRC Module ............. Cyclic Redundancy Check (CRC) Module Introduction ................... CRC Standard and Bit Order .................... CRC Checksum Generation ................... 9.3.1 CRC Implementation SLAU272C – May 2011 – Revised November 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 6 12.3.4 TBxCCRn Register ....................12.3.5 TBxIV Register ....................12.3.6 TBxEX0 Register ....................Real-Time Clock B (RTC_B) ................. 13.1 Real-Time Clock RTC_B Introduction Contents SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 7 14.2.6 Indirect Addressing of Result Registers ....................14.2.7 Using Interrupts ...................... 14.2.8 Using DMA ......................14.3 MPY32 Registers ..................14.3.1 MPY32CTL0 Register ........................REF Module SLAU272C – May 2011 – Revised November 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 8 Comparator_D Registers ....................17.3.1 CDCTL0 Register ....................17.3.2 CDCTL1 Register ....................17.3.3 CDCTL2 Register ....................17.3.4 CDCTL3 Register ....................17.3.5 CDINT Register Contents SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 9 19.4.2 UCAxBRW Register ..................19.4.3 UCAxSTATW Register ..................19.4.4 UCAxRXBUF Register ..................19.4.5 UCAxTXBUF Register ....................19.4.6 UCAxIE Register ..................... 19.4.7 UCAxIFG Register SLAU272C – May 2011 – Revised November 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 10 ................ 21.2.3 State Storage (Internal Trace Buffer) ....................21.2.4 Cycle Counter ....................21.2.5 Clock Control ..................... 21.3 EEM Configurations ........................Revision History Contents SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 11 PUSH SP, POP SP Sequence ........................4-9. SR Bits ................4-10. Register-Byte and Byte-Register Operation ....................4-11. Register-Word Operation ....................4-12. Word-Register Operation SLAU272C – May 2011 – Revised November 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 12 4-58. Swap Bytes SWPBX[.W] In Memory ....................4-59. Sign Extend SXTX.A ....................4-60. Sign Extend SXTX[.W] ..................5-1. FRAM Controller Block Diagram List of Figures SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 13 CRCRESR Register ..................10-1. Watchdog Timer Block Diagram ....................... 10-2. WDTCTL Register ....................11-1. Timer_A Block Diagram ........................11-2. Up Mode SLAU272C – May 2011 – Revised November 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 14 ...................... 13-5. RTCCTL3 Register ......................13-6. RTCSEC Register ......................13-7. RTCSEC Register ......................13-8. RTCMIN Register ......................13-9. RTCMIN Register List of Figures SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 15 ....................16-14. ADC10CTL2 Register ....................16-15. ADC10MEM0 Register ....................16-16. ADC10MEM0 Register ....................16-17. ADC10MCTL0 Register ....................... 16-18. ADC10HI Register SLAU272C – May 2011 – Revised November 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 16 19-4. eUSCI SPI Timing With UCMSB = 1 ....................19-5. UCAxCTLW0 Register ..................... 19-6. UCAxBRW Register ....................19-7. UCAxSTATW Register List of Figures SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 17 20-30. UCBxI2CSA Register ......................20-31. UCBxIE Register ....................... 20-32. UCBxIFG Register ......................20-33. UCBxIV Register ..................21-1. Large Implementation of EEM SLAU272C – May 2011 – Revised November 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 18 Interrupt, Return, and Reset Cycles and Length ..............4-9. MSP430 Format II Instruction Cycles and Length ..............4-10. MSP430 Format I Instructions Cycles and Length List of Tables SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 19 ................... 8-9. PxOUT Register Description .................... 8-10. P1DIR Register Description ................... 8-11. PxREN Register Description ................... 8-12. PxSEL0 Register Description SLAU272C – May 2011 – Revised November 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 20 ..................13-14. RTCDAY Register Description ..................13-15. RTCMON Register Description ..................13-16. RTCMON Register Description ..................13-17. RTCYEAR Register Description List of Tables SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 21 ..................17-4. CDCTL2 Register Description ..................17-5. CDCTL3 Register Description .................... 17-6. CDINT Register Description ....................17-7. CDIV Register Description SLAU272C – May 2011 – Revised November 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 22 ..................20-8. UCBxTBCNT Register Description ..................20-9. UCBxRXBUF Register Description ..................20-10. UCBxTXBUF Register Description ..................20-11. UCBxI2COA0 Register Description List of Tables SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 23 20-17. UCBxI2CSA Register Description ................... 20-18. UCBxIE Register Description ..................20-19. UCBxIFG Register Description ................... 20-20. UCBxIV Register Description ..................... 21-1. EEM Configurations SLAU272C – May 2011 – Revised November 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 24: Preface
Integer portion of N/2 Input/Output Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode; also named PM for Power Mode Memory Address Bus Read This First SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 25 Cleared by hardware Set by hardware -0,-1 Condition after PUC -(0),-(1) Condition after POR -[0],-[1] Condition after BOR -{0},-{1} Condition after Brownout SLAU272C – May 2011 – Revised November 2013 Read This First Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 26: System Resets, Interrupts, And Operating Modes, System Control Module (Sys)
..................1.14 Device Descriptor Table ....................1.15 SFR Registers ....................1.16 SYS Registers System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 27: System Control Module (Sys) Introduction
NOTE: The number and type of resets available may vary from device to device. See the device- specific data sheet for all reset sources available. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 28: Bor, Por, And Puc Reset Circuit
MCLK Module PUCs PUC Logic Figure 1-1. BOR, POR, and PUC Reset Circuit System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 29: Device Initial Conditions After System Reset
Module_C_int MAB - 6LSBs Module_D_int low priority Figure 1-2. Interrupt Priority SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 30: Non)Maskable Interrupts (Nmis)
Each individual peripheral interrupt is discussed in its respective module chapter in this manual. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 31: Interrupt Processing
CPU status register GIE bit must be considered in the same fashion. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 32: Interrupt Nesting
… Watchdog timer WDTIFG Maskable Device specific … … Reserved Maskable … Lowest System Resets, Interrupts, and Operating Modes, System Control Module (SYS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 33: Sys Interrupt Vector Generators
SYSRSTIV, SYSSNIV, SYSUNIV register automatically resets all pending interrupt flags of the group. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 34 ; Return SBD_ISR: ; Vector 22 ; Task_22 starts here RETI ; Return System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 35: Operating Modes
(for example, MSP-FET430UIF). See the PMM and SVS chapter for further details. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 36: Operation Modes
‡ An enabled reset always restarts the device Arbitrary transitions Figure 1-5. Operation Modes System Resets, Interrupts, and Operating Modes, System Control Module (SYS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 37: Low-Power Modes And Clock Requests
LPM1 LPM2 LPM2 LPM2 LPM0 LPM3 LPM3 LPM3 LPM1 LPM4 LPM4 LPM3 LPM1 SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 38: Entering And Exiting Low-Power Modes Lpm0 Through Lpm4
RTC mode available. In addition to the wakeup events possible in LPM4.5, RTC wakeup events are also possible in LPM3.5. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 39: Principles For Low-Power Applications
If the application has low duty cycle and slow response time events, maximizing time in LPMx.5 can further reduce power consumption significantly. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 40: Connection Of Unused Pins
Therefore, SYSJTAGPIN is a write only once function. Clearing it by software is not possible, and the device does not change from four-wire JTAG mode to general-purpose I/O. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 41: Vacant Memory Space
Providing entry password for device lock or unlock protection • Run-time data exchange (RTDX) SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 42: Jmb Configuration
Signature 1 (memory location 0FF80h) and JTAG Signature 2 (memory location 0FF82h) control the behavior of the device locking mechanism. NOTE: When a device has been protected, Texas Instruments cannot access the device for a customer return. Access is only possible if a BSL is provided with its corresponding key or an unlock mechanism is provided by the customer.
Page 43: Jtag And Sbw Lock Without Password
The complete device descriptor table and its contents can be found in the device-specific data sheet. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 44: Identifying Device Type
For example, if Info_length = 5, then the length of the descriptors equals 128 bytes. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 45: Tlv Descriptors
// No TLV descriptor found with a matching d_ID_value Return a failing condition SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 46: Calibration Values
Divide the result by 2 : 0x00F7_7600 / 0x0001_0000 = 0x0000_00F7 = 247 decimal System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 47: Adc Calibration Tags
TLV structure. The characteristic equation of the temperature sensor voltage, in millivolts is: Temp ´ SENSE SENSOR SENSOR SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 48: Bsl Configuration Tags
The interpretation is shown in Table 1-10. Unused bytes in BSL_CIF_CONFIG are defined as 00h. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 49: Sfr Registers
Reset Pin Control Read/write Word 000Ch Section 1.15.3 SFRRPCR_L Read/write Byte SFRRPCR_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 50: Sfrie1 Register
MOV.B or CLR.B instruction. 0b = Interrupts disabled 1b = Interrupts enabled System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 51: Sfrifg1 Register
Oscillator fault interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 52 WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 53: Sfrrpcr Register
NMI select. This bit selects the function for the RST/NMI pin. 0b = Reset function 1b = NMI function SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 54: Sys Registers
Word 0000h Section 1.16.8 SYSRSTIV Reset Vector Generator Read Word 0002h Section 1.16.9 System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 55: Sysctl Register
1b = Interrupt vectors generated with end address TOP of RAM, when RAM available. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 56: Sysjmbc Register
0b = JMBI1 has no new data. 1b = JMBI1 has new data available. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 57: Sysjmbi0 Register
JTAG mailbox incoming message high byte MSGLO JTAG mailbox incoming message low byte SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 58: Sysjmbo0 Register
JTAG mailbox outgoing message high byte MSGLO JTAG mailbox outgoing message low byte System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 59: Sysuniv Register
NMI flags. See the device-specific data sheet for a list of values. SLAU272C – May 2011 – Revised November 2013 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 60: Sysrstiv Register
See the device-specific data sheet for a list of values. Reset value depends on reset source. System Resets, Interrupts, and Operating Modes, System Control Module SLAU272C – May 2011 – Revised November 2013 (SYS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 61: Power Management Module And Supply Voltage Supervisor
Supply Voltage Supervisor (SVS)..........................Topic Page ........... Power Management Module (PMM) Introduction ....................PMM Operation ....................PMM Registers SLAU272C – May 2011 – Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 62: Power Management Module (Pmm) Introduction
The block diagram of the PMM is shown in Figure 2-1. CORE Reference SVSH SVSL Brownout Figure 2-1. PMM Block Diagram Power Management Module and Supply Voltage Supervisor SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 63: Pmm Operation
H_IT- CORE _IT+ L_IT- Time Figure 2-2. High-Side and Low-Side Voltage Failure and Resulting PMM Actions SLAU272C – May 2011 – Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 64: Supply Voltage Supervisor - Power-Up
The external RST/NMI terminal is pulled low on a BOR reset condition. The RST/NMI can be used as reset source for the rest of the application. Power Management Module and Supply Voltage Supervisor SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 65: Pmm Interrupts
During the undervoltage event, external voltage changes on the pin are not registered internally. This helps prevent erratic behavior from occurring. SLAU272C – May 2011 – Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 66: Pmm Registers
Power mode 5 control register 0 Read/write Word 0000h Section 2.3.3 PM5CTL0_L Read/write Byte PM5CTL0_H Read/write Byte Power Management Module and Supply Voltage Supervisor SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 67: Pmmctl0 Register
Software brownout reset. Setting this bit to 1 triggers a BOR. This bit is self clearing. Reserved Reserved. Always reads as 0. Reserved Reserved. Must always be written as 0. SLAU272C – May 2011 – Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 68: Pmmifg Register
0b = Reset not due to SWBOR 1b = Reset due to SWBOR Reserved Reserved. Always reads as 0. Power Management Module and Supply Voltage Supervisor SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 69: Pm5Ctl0 Register
0b = LPMx.5 configuration is not locked and defaults to its reset condition. 1b = LPMx.5 configuration remains locked. Pin state is held during LPMx.5 entry and exit. SLAU272C – May 2011 – Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 70: Clock System (Cs)
This chapter describes the operation of the clock system, which is implemented in all devices..........................Topic Page ................. Clock System Introduction ..................Clock System Operation ................Module Oscillator (MODOSC) ..................... CS Registers Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 71: Clock System Introduction
MODCLK: Module clock. MODCLK is used by various peripheral modules and is sourced by MODOSC. Figure 3-1 shows a block diagram of the clock system module. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 72: Clock System Block Diagram
Optional module Unconditonal MODOSC requests . † Not available on all devices MODCLK MODOSC Figure 3-1. Clock System Block Diagram Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 73: Clock System Operation
XT1BYPASS = 1. When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT1 is powered down when used in bypass mode. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 74: Xt2 Oscillator
DCORSEL bits causes the DCOCLK to be held for four clock cycles before releasing the new value into the system. This allows for the DCO to settle properly. Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 75: Operation From Low-Power Modes, Requested By Peripheral Modules
SMCLKREQEN for the respective clocks. This does not disable fail-safe clock requests; for example, those of the watchdog timer or the clock system itself. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 76: Cs Module Fail-Safe Operation
The fail-safe logic does not change the respective SELA, SELM, and SELS bit settings. The fail-safe mechanism behaves the same in normal and bypass modes. Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 77: Oscillator Fault Logic
OFIFG signal. If no fault condition remains when the OFIFG signal is cleared, the clock logic switches back to the original user settings prior to the fault condition. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 78: Synchronization Of Clock Signals
ADC10OSC clock source. Upon doing so, the MODOSC source is enabled, if not already enabled from other modules' previous requests. Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 79: Cs Registers
Byte CSCTL5_H Read/write Byte CSCTL6 Clock System Control 6 Read/write Word 0007h Section 3.4.7 CSCTL6_L Read/write Byte CSCTL6_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 80: Csctl0 Register
PUC is generated Reserved Reserved. Always reads as 0. Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 81: Csctl1 Register
If DCORSEL = 1: 00b = 16 01b = 20 10b = 16 11b = 24 Reserved Reserved. Always reads as 1. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 82: Csctl2 Register
110b = Reserved. Defaults to XT2CLK when available, otherwise DCOCLK. 111b = Reserved. Defaults to XT2CLK when available, otherwise DCOCLK. Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 83: Csctl3 Register
011b = f(MCLK)/8 100b = f(MCLK)/16 101b = f(MCLK)/32 110b = Reserved. Defaults to f(MCLK)/32. 111b = Reserved. Defaults to f(MCLK)/32. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 84: Csctl4 Register
1b = XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 85: Csctl5 Register
0b = No fault condition occurred after the last reset. 1b = XT1 fault (LF mode or HF mode). A XT1 fault occurred after the last reset. SLAU272C – May 2011 – Revised November 2013 Clock System (CS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 86: Csctl6 Register
ACLK clock request enable. Setting this enables conditional module requests for ACLK. 0b = ACLK conditional requests are disabled 1b = ACLK conditional requests are enabled Clock System (CS) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 87: Cpux
..............MSP430X CPU (CPUX) Introduction ......................Interrupts ....................CPU Registers .................... Addressing Modes ..............MSP430 and MSP430X Instructions ................Instruction Set Description SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 88: Msp430X Cpu (Cpux) Introduction
Direct memory-to-memory transfers without intermediate register holding • Byte, word, and 20-bit address-word addressing The block diagram of the MSP430X CPU is shown in Figure 4-1. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 89: Msp430X Cpu Block Diagram
General Purpose General Purpose General Purpose General Purpose Zero, Z Carry, C MCLK 16/20-bit ALU Overflow,V Negative,N Figure 4-1. MSP430X CPU Block Diagram SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 90: Interrupts
20-bit PC is restored making return from interrupt to any address in the memory range possible. Item n-1 PC.15:0 PC.19:16 SR.11:0 Figure 4-2. PC Storage on the Stack for Interrupts CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 91: Cpu Registers
Figure 4-5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 92: Stack Pointer
The POP SP instruction places SP1 into the stack pointer SP (SP2 = SP1) Figure 4-8. PUSH SP, POP SP Sequence CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 93: Status Register (Sr)
Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and BIC. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 94: Constant Generator Registers (Cg1 And Cg2)
#0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD #1,dst CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 95: General-Purpose Registers (R4 To R15)
Register-Word Operation High Byte Low Byte 19 16 15 Register used Memory Operation Memory Figure 4-11. Register-Word Operation SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 96: Word-Register Operation
High Byte Low Byte 19 16 15 Register Memory +2 Unused Memory Operation Memory +2 Memory Figure 4-13. Register – Address-Word Operation CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 97: Addressing Modes
Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels and have no special meaning. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 98: Register Mode
Register Space Space 21036h xxxxh AA550h 21036h xxxxh AA550h 11111h BB551h 21034h D546h 21034h D546h 21032h 1800h 21032h 1800h AA550h.or.11111h = BB551h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 99: Indexed Mode
The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 100: Indexed Mode In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 4-16. Indexed Mode in Upper Memory CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 101: Overflow And Underflow For Indexed Mode
23456h + F8346h = 1B79Ch. Destination: The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 102: Example For Indexed Mode
Two words pointed to by R5 + 12346h which results in address 23456h + 12346h = 3579Ch. Destination: Two words pointed to by R6 + 32100h which results in address 45678h + 32100h = 77778h. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 103: Symbolic Mode
64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4-19. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 104: Symbolic Mode Running In Lower 64 Kb
Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the index for this example. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 105: Symbolic Mode Running In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 4-20. Symbolic Mode Running in Upper Memory SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 106: Overflow And Underflow For Symbolic Mode
3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this example. Destination: Word TONI located at address 00778h pointed to by the absolute address 00778h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 107 Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit result of 77778h – 21038h = 56740h. Address 21038h is the address of the index in this example. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 108: Absolute Mode
This instruction adds the 16-bit data contained in the absolute source and destination addresses and places the result into the destination. Source: Word at address EDE Destination: Word at address TONI CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 109 Source: Two words beginning with address EDE Destination: Two words beginning with address TONI SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 110: Indirect Register Mode
Word pointed to by R5. R5 contains address 3579Ch for this example. Destination: Word pointed to by R6 + 2100h, which results in address 45678h + 2100h = 7778h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 111: Indirect Autoincrement Mode
Byte pointed to by R5. R5 contains address 3579Ch for this example. Destination: Byte pointed to by R6 + 0h, which results in address 0778h for this example SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 112: Immediate Mode
This instruction adds the 16-bit immediate operand 3456h to the data in the destination address TONI. Source: 16-bit immediate value 3456h Destination: Word at address TONI CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 113 3456h 21036h 3456h 50F2h 50F2h 21034h 21034h 1907h 1907h 21032h 21032h 23456h 7777Ah 0001h 7777Ah 0003h +12345h 3579Bh 2345h 579Bh 77778h 77778h SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 114: Msp430 And Msp430X Instructions
12 MSP430 double-operand instructions. Op-code Rsrc Ad B/W Rdst Source or Destination 15:0 Destination 15:0 Figure 4-22. MSP430 Double-Operand Instruction Format CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 115: Msp430 Single-Operand Instructions
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 116: Format Of Conditional Jump Instructions
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. 116 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 117: Interrupt, Return, And Reset Cycles And Length
Instruction PUSH CALL SWPB, SXT SWPB R5 RRC @R9 @Rn+ SWPB @R10+ CALL #LABEL X(Rn) CALL 2(R7) PUSH EDE &EDE SXT &EDE SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 118: Msp430 Format I Instructions Cycles And Length
MOV &EDE,R8 BR &EDE TONI MOV &EDE,TONI x(Rm) MOV &EDE,0(SP) &TONI MOV &EDE,&TONI MOV, BIT, and CMP instructions execute in one fewer cycle. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 119: Msp430X Extended Instructions
Table 4-12. An example is shown in Figure 4-28. Source bits 19:16 Destination bits 19:16 Figure 4-26. Extension Word for Non-Register Modes SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 120: Example For Extended Register Or Register Instruction
8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 4-27. Example for Extended Register or Register Instruction CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 121: Example For Extended Immediate Or Indexed Instruction
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 122: Extended Format I Instruction Formats
Figure 4-30..................19:16 Address+2 Address Operand LSBs 15:0 Figure 4-30. 20-Bit Addresses in Memory CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 123: Extended Format Ii Instruction Format
The three possible addressing mode combinations for Format II instructions are shown in Figure 4-31. n-1/Rn Op-code Op-code dst.19:16 Op-code dst.15:0 Figure 4-31. Extended Format II Instruction Format SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 124: Pushm And Popm Instruction Format
Figure 4-34. BRA Instruction Format Op-code Rdst Op-code Rdst index15:0 Op-code #imm/ix/abs19:16 #imm15:0 / index15:0 / &abs15:0 Figure 4-35. CALLA Instruction Format CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 125: Extended Emulated Instructions
Test Rdst (compare with 0) CMPA #0,Rdst TSTX(.B,.A) dst Test dst (compare with 0) CMPX(.B,.A) #0,dst POPX dst Pop to dst MOVX(.B, .A) @SP+,dst SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 126: Address Instructions, Operate On 20-Bit Register Data
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 127: Msp430X Format Ii Instruction Cycles And Length
5, 3 5, 3 POPX.A 4, 2 – – – 7, 3 7, 3 7, 3 Add one cycle when Rn = SP SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 128: Msp430X Format I Instruction Cycles And Length
Reduce the cycle count by two for MOV, BIT, and CMP instructions. Reduce the cycle count by one for MOV, ADD, and SUB instructions. 128 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 129: Address Instruction Cycles And Length
MOVA 2(R5),R8 – – MOVA 2(R6),PC – – MOVA EDE,R8 – – MOVA EDE,PC &EDE – – MOVA &EDE,R8 – – MOVA &EDE,PC SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 130: Instruction Set Description
SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx BIC, BIC.B Dxxx BIS, BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 131: Extended Instruction Binary Descriptions
– 1 RRCM.W #n,Rdst RRAM.W RRAM.W #n,Rdst n – 1 RLAM.W n – 1 RLAM.W #n,Rdst RRUM.W RRUM.W #n,Rdst n – 1 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 132 POPM.A n – 1 dst – n + 1 POPM.A #n,Rdst POPM.W n – 1 dst – n + 1 POPM.W #n,Rdst CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 133: Msp430 Instructions
Instruction Set Description www.ti.com 4.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 134 The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 135 The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B @R5+,R6 ; Add byte to R6. R5 + 1. R6: 000xxh TONI ; Jump if no carry ; Carry occurred SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 136 ADDC.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 137 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 138 A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 139 A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 140 ; Test I/O port P1 bits. R5 + 1 TONI ; No corresponding bit is set ; At least one bit is set CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 141 ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 142 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL ; Start address at @R5 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 143 TONI ; 0 -> TONI Example Register R5 is cleared. Example RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 144 @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter DADC 2(R12) ; add carry to high word of 32-bit counter CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 145 CLRN CALL SUBR .... SUBR SUBRET ; If input is negative: do nothing and return ....SUBRET SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 146 (R5 + X); for example, a table with addresses starting at X. The address is within the lower 64 KB. X is within ±32 KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 147 Jump to label TONI if values are equal. The next table byte is addressed. CMP.B @R5+,&P1OUT ; Compare P1 bits with table. R5 + 1 TONI ; Equal contents ; Not equal SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 148 ; Reset carry ; next instruction's start condition is defined DADD.B R5,0(R8) ; Add LSDs + C DADC 1(R8) ; Add carry to MSDs CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 149 BCD number contained in R4. The carry C is added, also. R4.19:8 = 0 CLRC ; Clear carry DADD.B &BCD,R4 ; Add BCD to R4 decimally. R4: 0,00ddh SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 150: Decrement Overlap
Do not transfer tables using the routine above with the overlap shown in Figure 4-36. TONI EDE+254 TONI+254 Figure 4-36. Decrement Overlap CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 151 DECD Example Memory at location LEO is decremented by two. DECD.B ; Decrement MEM(LEO) Decrement status byte STATUS by two DECD.B STATUS SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 152 EINT and DINT. Note that any alternative instruction use that sets and immediately clears the CPU status register GIE bit must be considered in the same fashion. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 153 EINT and DINT. Note that any alternative instruction use that sets and immediately clears the CPU status register GIE bit must be considered in the same fashion. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 154 The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B STATUS CMP.B #11,STATUS OVFL CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 155 The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 156 Content of memory byte LEO is negated. MOV.B #0AEh,LEO MEM(LEO) = 0AEh INV.B ; Invert LEO, MEM(LEO) = 051h INC.B ; MEM(LEO) is negated, MEM(LEO) = 052h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 157 ; Is R5 >= 12345h? Info to C Label2 ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 158 R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA #1,R7 ; Increment R7 Label4 ; Zero reached: Go to Label4 ; R7 not equal 0. Continue here. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 159 CMPA #12345h,R5 ; Is R5 >= 12345h? Label2 ; Yes, 12344h < R5 <= 7FFFFh ; No, 80000h <= R5 < 12345h SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 160 CMPA #12345h,R5 ; Is R5 < 12345h? Label2 ; Yes, 80000h =< R5 < 12345h ; No, 12344h < R5 <= 7FFFFh CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 161 ; No Timer_A interrupt pending IHCCR1 ; Timer block 1 caused interrupt IHCCR2 ; Timer block 2 caused interrupt RETI ; No legal interrupt, return SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 162 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; R7 < 0: Go to Label4 ; R7 >= 0. Continue here. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 163 TONI is within PC ± 32 K. TONI,R5 ; TONI + R5 -> R5. Carry -> C Label0 ; No carry ; Carry = 1: continue here SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 164 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 165 Loop MOV.B @R10+,TOM-EDE-1(R10) ; R10 points to both tables. ; R10+1 ; Decrement counter Loop ; Not yet done ; Copy completed SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 166 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 167 ; Last word on stack moved to the SR NOTE: System stack pointer The system SP is always incremented by two, independent of the byte suffix. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 168 Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B ; Save EDE xxXXh PUSH.B TONI ; Save TONI xxYYh CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 169: Stack After A Ret Instruction
; Return to lower 64 K Item n Item n Return Stack before RET Stack after RET instruction instruction Figure 4-37. Stack After a RET Instruction SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 170 ; Interrupt handler code POPM.A #2,R14 ; Restore R13 and R14 (20-bit data) RETI ; Return to 20-bit address in full memory range CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 171: Destination Operand-Arithmetic Shift Left
The assembler does not recognize the instructions: @R5+ RLA.B @R5+ RLA(.B) @R5 They must be substituted by: @R5+,-2(R5) ADD.B @R5+,-1(R5) ADD(.B) @R5 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 172: Destination Operand-Carry Left Shift
The assembler does not recognize the instructions: @R5+ RLC.B @R5+ RLC(.B) @R5 They must be substituted by: ADDC @R5+,-2(R5) ADDC.B @R5+,-1(R5) ADDC(.B) @R5 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 173: Rotate Right Arithmetically Rra.b And Rra.w
The signed RAM byte EDE is shifted arithmetically right one position. RRA.B ; EDE/2 -> EDE Figure 4-40. Rotate Right Arithmetically RRA.B and RRA.W SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 174: Rotate Right Through Carry Rrc.b And Rrc.w
; Prepare carry for MSB ; EDE = EDE >> 1 + 8000h Figure 4-41. Rotate Right Through Carry RRC.B and RRC.W CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 175 ; Subtract LSDs SBC.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 176 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 177 The negative bit (N) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 178 The zero bit (Z) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 179 Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 180 Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64 K. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 181: Swap Bytes In Memory
Figure 4-42. Swap Bytes in Memory Before SWPB High Byte Low Byte After SWPB Low Byte High Byte Figure 4-43. Swap Bytes in a Register SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 182 R7. MOV.B EDE,R5 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ADDA R5,R7 ; Add signed 20-bit values CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 183 ; Low byte of R7 is positive but not zero R7NEG ..; Low byte of R7 is negative R7ZERO ..; Low byte of R7 is zero SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 184 R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B EDE,R7 ; Set different bits to 1 in R7. INV.B ; Invert low byte of R7, high byte is 0h CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 185: Extended Instructions
20-bit values when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 186 The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A @R12 ; Increment lower 20 bits ADCX.A @R13 ; Add carry to upper 20 bits CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 187 ; Jump if no carry ; Carry occurred Note: Use ADDA for the following two cases for better code density and execution. ADDX.A Rsrc,Rdst ADDX.A #imm20,Rdst SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 188 ADDCX.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 189 A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 190 A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 191 A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 192 ; Test input P1 bits. R5 + 1 TONI ; No corresponding input bit is set ; At least one bit is set CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 193 Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is cleared. CLRX.A TONI ; 0 -> TONI SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 194 ; Equal contents ; Not equal Note: Use CMPA for the following two cases for better density and execution. CMPA Rsrc,Rdst CMPA #imm20,Rdst CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 195 The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) ; Increment lower 20 bits DADCX.A 0(R13) ; Add carry to upper 20 bits SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 196 The two-digit BCD number contained in 20-bit address BCD is added decimally to a two- digit BCD number contained in R4. CLRC ; Clear carry DADDX.B BCD,R4 ; Add BCD to R4 decimally. ; R4: 000ddh CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 197 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by one. DECX.A TONI ; Decrement TONI SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 198 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by two. DECDX.A TONI ; Decrement TONI CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 199 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-wordTONI is incremented by one. INCX.A TONI ; Increment TONI (20-bits) SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 200 OSCOFF, CPUOFF, and GIE are not affected. Example RAM byte LEO is incremented by two; PC points to upper memory. INCDX.B ; Increment LEO by two CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 201 Content of memory byte LEO is negated. PC is pointing to upper memory. INVX.B ; Invert LEO INCX.B ; MEM(LEO) is negated SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 202 MOVA &abs20,Rdst ; Absolute/Reg MOVX.A @Rsrc,Rdst MOVA @Rsrc,Rdst ; Indirect/Reg MOVX.A @Rsrc+,Rdst MOVA @Rsrc+,Rdst ; Indirect,Auto/Reg MOVX.A Rsrc,&abs20 MOVA Rsrc,&abs20 ; Reg/Absolute CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 203 MOVA z16(Rsrc),Rdst ; Indexed/Reg MOVX.A Rsrc,z20(Rdst) MOVA Rsrc,z16(Rdst) ; Reg/Indexed MOVX.A symb20,Rdst MOVA symb16,Rdst ; Symbolic/Reg MOVX.A Rsrc,symb20 MOVA Rsrc,symb16 ; Reg/Symbolic SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 204 Example Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 205 Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 206 &EDE ; Write word to address EDE Example Write the 20-bit value on TOS to R9 POPX.A ; Write address-word to R9 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 207 ; Save byte at address EDE Example Save the 20-bit value in R9 on the stack. PUSHX.A ; Save address-word in R9 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 208: Rotate Left Arithmetically-Rlam[.W] And Rlam.a
The 20-bit operand in R5 is shifted left by three positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 0000 Figure 4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 209: Destination Operand-Arithmetic Shift Left
Example The 20-bit value in R7 is multiplied by 2 RLAX.A ; Shift left R7 (20-bit) Figure 4-45. Destination Operand-Arithmetic Shift Left SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 210: Destination Operand-Carry Left Shift
The RAM byte LEO is shifted left one position. PC is pointing to upper memory. RLCX.B ; RAM(LEO) x 2 + C -> RAM(LEO) Figure 4-46. Destination Operand-Carry Left Shift CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 211: Rotate Right Arithmetically Rram[.W] And Rram.a
#1,R15 ; (1.5 y R15) y 0.5 = 0.75 y R15 -> R15 0000 Figure 4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 212 The signed 20-bit number in R5 is shifted arithmetically right four positions. RRAX.A ; R5/16 -> R5 Example The signed 8-bit value in EDE is multiplied by 0.5. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 213: Rotate Right Arithmetically Rrax(.B,.A) - Register Mode
; EDE/2 -> EDE 0000 Figure 4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode Figure 4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 214 Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) Reset Mode Bits OSCOFF, CPUOFF, and GIE are not affected. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 215: Rotate Right Through Carry Rrcm[.W] And Rrcm.a
MSB–1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 Figure 4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 216 ; Prepare carry for MSB RRCX.A ; EDE = EDE » 1 + 80000h Example The word in R6 is shifted right by 12 positions. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 217: Rotate Right Through Carry Rrcx(.B,.A) - Register Mode
0 - - - - - - - - - - - - - - - - - - - - 0 Figure 4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode Figure 4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 218: Rotate Right Unsigned Rrum[.W] And Rrum.a
The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 0000 Figure 4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 219: Rotate Right Unsigned Rrux(.B,.A) - Register Mode
0 - - - - - - - - - - - - - - - - - - - - 0 Figure 4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 220 ; Subtract LSDs SBCX.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 221 ; Subtract CNT from @R12 Note: Use SUBA for the following two cases for better density and execution. SUBX.A Rsrc,Rdst SUBX.A #imm20,Rdst SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 222 Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 223: Swap Bytes Swpbx.a Register Mode
Figure 4-55. Swap Bytes SWPBX.A Register Mode Before SWPBX.A High Byte Low Byte After SWPBX.A Low Byte High Byte Figure 4-56. Swap Bytes SWPBX.A In Memory SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 224: Swap Bytes Swpbx[.W] Register Mode
Figure 4-57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX High Byte Low Byte After SWPBX Low Byte High Byte Figure 4-58. Swap Bytes SWPBX[.W] In Memory CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 225: Sign Extend Sxtx.a
8 7 6 SXTX.A dst 8 7 6 ..Figure 4-59. Sign Extend SXTX.A SXTX[.W] Rdst SXTX[.W] dst Figure 4-60. Sign Extend SXTX[.W] SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 226 ; LEO is zero LEOPOS ..; LEO is positive but not zero LEONEG ..; LEO is negative LEOZERO ..; LEO is zero CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 227 (20-bit address) XORX.B EDE,R7 ; Set different bits to 1 in R7 INV.B ; Invert low byte of R7. R7.19:8 = 0. SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 228: Address Instructions
MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. The MSP430X address instructions are listed and described in the following pages. CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 229 R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA #0A4320h,R5 ; Add A4320h to 20-bit R5 TONI ; Jump on carry ; No carry occurred SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 230 Indirect mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. ; MOVA @R5,PC CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 231 Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 232 Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA ; Start address at @R5 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 233 LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 + 32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 234 The destination register is cleared. Status Bits Status bits are not affected. Example The 20-bit value in R10 is cleared. CLRA ; 0 -> R10 CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 235 R6, the program continues at label GRE. CMPA R6,R5 ; Compare R6 with R5 (R5 - R6) ; R5 >= R6 ; R5 < R6 SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 236 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is decremented by 2. DECDA ; Decrement R5 by two CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 237 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is incremented by two. INCDA ; Increment R5 by two SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 238 Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 239 Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ± 32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 240 ; Save R14 and R13 (20 bit data) ; Subroutine code POPM.A #2,R14 ; Restore R13 and R14 (20 bit data) RETA ; Return (to full address space) CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 241 The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA R5,R6 ; R6 - R5 -> R6 TONI ; Carry occurred ; No carry SLAU272C – May 2011 – Revised November 2013 CPUX Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 242 ; R7 is zero R7POS ..; R7 is positive but not zero R7NEG ..; R7 is negative R7ZERO ..; R7 is zero CPUX SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 243: Fram Controller (Frctl)
FRAM Organization ................. FRCTL Module Operation ..............Programming FRAM Memory Devices .................... Wait State Control ...................... FRAM ECC ..................... FRCTL Registers SLAU272C – May 2011 – Revised November 2013 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 244: Fram Introduction
System Reset event (SYSRST) can be generated by setting the UBDRSTEN bit. If an uncorrectable error is detected, a PUC is initiated and the program vectors to the SYSRSTIV. FRAM Controller (FRCTL) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 245: Programming Fram Memory Devices
FRAM cycle time requirement. . Table 5-1 lists the NACCESS and NPRECHG settings based on some common frequencies of MCLK. SLAU272C – May 2011 – Revised November 2013 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 246: Automatic Wait State Control
UBDIEN enables a NMI event if an uncorrectable bit error is detected. CBDIEN enables a NMI event if a correctable bit error is detected and corrected. FRAM Controller (FRCTL) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 247: Frctl Registers
Read/Write Byte GCCTL0_H Read/Write Byte GCCTL1 General Control 1 Read/write Word 0000h Section 5.7.3 GCCTL1_L Read/Write Byte GCCTL1_H Read/Write Byte SLAU272C – May 2011 – Revised November 2013 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 248: Frctl0 Register
Wait state generator precharge time control. Each wait state adds a N integer multiple increase of the IFCLK period where N = 0 through 7. N = 0 implies no wait states. FRAM Controller (FRCTL) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 249: Gcctl0 Register
Enable NMI event if Access time error occurs. 0b = Access violation interrupt disabled 1b = Access violation interrupt enabled Reserved Reserved. Always reads as 0. SLAU272C – May 2011 – Revised November 2013 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 250: Gcctl1 Register
0b = No interrupt pending 1b = Interrupt pending. Can be cleared by user or by reading SYSSNIV. Reserved Reserved. Always reads as 0. FRAM Controller (FRCTL) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 251: Memory Protection Unit (Mpu)
Memory Protection Unit (MPU) Introduction ....................MPU Segments ..............MPU Access Management Settings ....................MPU Violations ....................MPU Registers SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 252: Memory Protection Unit (Mpu) Introduction
An overview of the MPU is shown in Figure 6-1. Control Registers Main Memory Array/ Violation Controller Figure 6-1. Memory Protection Unit Overview Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 253: Mpu Segments
512 bytes in a 16KB device, 256 bytes in a 8KB device, and 128 bytes in a 4KB device. SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 254: Page Addresses For 16Kb, 8Kb, And 4Kb Main Memory
FA00h FBFFh FD00h FDFFh FE80h FEFFh FC00h FDFFh FE00h FEFFh FF00h FF7Fh FE00h FFFFh FF00h FFFFh FF80h FFFFh 254 Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 255: Information Memory
MPU. Table 6-2. Segment Access Rights MPUSEGxXE MPUSEGxWE MPUSEGxRE Execute Rights Write Rights Read Rights SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 256: Mpu Violations
Upon an access rights violation, the data bus content (MDB) is driven with 03FFFh until the next valid data is available. Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 257: Mpu Registers
Byte MPUIV Memory Protection Unit Interrupt Vector Read/write Word 0000h Section 6.5.5 Register MPUIV_L Read/Write Byte MPUIV_H Read/Write Byte SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 258: Mpuctl0 Register
MPU enable. This bit enables the MPU operation. This bit can be set any time with word write and the correct password. 0b = Disabled 1b = Enabled Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 259: Mpuctl1 Register
This bit is write 0 only. Write 1 has no effect. 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 260: Mpuseg Register
MPU segment border 1. After BOR, these bits are automatically set to 0 and only segment 3 is active. Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 261: Mpusam Register
0b = Violation in main memory segment 2 asserts the MPUSEG2IFG bit. 1b = Violation in main memory segment 2 asserts the MPUSEG2IFG bit and a PUC is executed. SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 262 0b = Reads of main memory segment 1 cause a violation if MPUSEG1WE = MPUSEG1XE = 0 1b = Reads of main memory segment 1 are allowed Memory Protection Unit (MPU) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 263: Mpuiv Register
06h = Interrupt Source: SEG2 Violation; Interrupt Flag: SEG2IFG 08h = Interrupt Source: SEG3 Violation; Interrupt Flag: SEG3IFG; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 264: Dma Controller
CPU intervention. This chapter describes the operation of the DMA controller..........................Topic Page ............Direct Memory Access (DMA) Introduction ....................DMA Operation ....................DMA Registers DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 265: Direct Memory Access (Dma) Introduction
• Four addressing modes • Single, block, or burst-block transfer modes The DMA controller block diagram is shown in Figure 7-1. SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 266: Dma Controller Block Diagram
DMAnSA DMAnTRIG0 00000 DMAnTRIG1 00001 DMAnDA DMAnSZ DMASRSBYTE DMAEN DMASRCINCR DMARMWDIS DMAnTRIG31 11111 Halt CPU Figure 7-1. DMA Controller Block Diagram DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 267: Dma Operation
Address Space Controller Controller Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses Figure 7-2. DMA Addressing Modes SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 268: Dma Transfer Modes
A complete block is transferred with one trigger. DMAEN remains enabled. 110, 111 Repeated burst-block transfer CPU activity is interleaved with a block transfer. DMAEN remains enabled. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 269: Dma Single Transfer State Diagram
AND Trigger = 0] AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 7-3. DMA Single Transfer State Diagram SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 270 In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer starts another block transfer. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 271: Dma Block Transfer State Diagram
DMAxSZ > 0 [DMALEVEL = 1 AND Trigger = 0] Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 7-4. DMA Block Transfer State Diagram SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 272 DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated burst- block mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 273: Dma Burst-Block Transfer State Diagram
AND DMAxSZ = 0] 2 × MCLK Burst State (release CPU for 2 × MCLK) Figure 7-5. DMA Burst-Block Transfer State Diagram SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 274 When DMALEVEL = 1, transfer modes selected when DMADT = {0, 1, 2, 3} are recommended, because the DMAEN bit is automatically reset after the configured transfer. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 275: Dma Trigger Operation
DMA0-DMA1-DMA2, for example, for three channels. When the ROUNDROBIN bit is cleared, the channel priority returns to the default priority. SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 276: Maximum Single-Transfer Dma Cycle Time
DMAIV register, DMA0IFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the DMA2IFG generates another interrupt. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 277 C module can trigger a transfer when new I C data is received and the when the transmit data is needed. SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 278 ADC10IFG0 is set. Setting the ADC10IFG0 with software does not trigger a transfer. The ADC10IFG0 flag is automatically reset when the ADC10MEM0 register is accessed by the DMA controller. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 279: Dma Registers
DMA Channel 6 Destination Address Read/write Word, undefined Section 7.3.8 double word DMA6SZ DMA Channel 6 Transfer Size Read/write Word undefined Section 7.3.9 SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 280 DMA Channel 7 Destination Address Read/write Word, undefined Section 7.3.8 double word DMA7SZ DMA Channel 7 Transfer Size Read/write Word undefined Section 7.3.9 DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 281: Dmactl0 Register
00000b = DMA0TRIG0 00001b = DMA0TRIG1 00010b = DMA0TRIG2 ⋮ 11110b = DMA0TRIG30 11111b = DMA0TRIG31 SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 282: Dmactl1 Register
00000b = DMA2TRIG0 00001b = DMA2TRIG1 00010b = DMA2TRIG2 ⋮ 11110b = DMA2TRIG30 11111b = DMA2TRIG31 DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 283: Dmactl2 Register
00000b = DMA4TRIG0 00001b = DMA4TRIG1 00010b = DMA4TRIG2 ⋮ 11110b = DMA4TRIG30 11111b = DMA4TRIG31 SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 284: Dmactl3 Register
00000b = DMA6TRIG0 00001b = DMA6TRIG1 00010b = DMA6TRIG2 ⋮ 11110b = DMA6TRIG30 11111b = DMA6TRIG31 DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 285: Dmactl4 Register
DMAABORT is set. 0b = NMI does not interrupt DMA transfer 1b = NMI interrupts a DMA transfer SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 286: Dmaxctl Register
0b = Edge sensitive (rising edge) 1b = Level sensitive (high level) DMAEN DMA enable 0b = Disabled 1b = Enabled DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 287 1b = DMA transfer interrupted by NMI DMAREQ DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0b = No DMA start 1b = Start DMA SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 288: Dmaxsa Register
Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxSA with word instructions, bits 19-16 are cleared. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 289: Dmaxda Register
Reading or writing bits 19–16 requires the use of extended instructions. When writing to DMAxDA with word instructions, bits 19–16 are cleared. SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 290: Dmaxsz Register
0001h = One byte or word is transferred. 0002h = Two bytes or words are transferred. ⋮ FFFFh = 65535 bytes or words are transferred. DMA Controller SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 291: Dmaiv Register
0Eh = Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG 10h = Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 DMA Controller Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 292: I/O Configuration
This chapter describes the operation of the digital I/O ports in all devices..........................Topic Page ..................Digital I/O Introduction ..................Digital I/O Operation ..................... I/O Configuration ..................Digital I/O Registers Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 293 PB, PC, PD, PE, and PF behave similarly. When reading from ports that contain fewer than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 294 PxDIR, PxREN, and PxOUT for proper I/O configuration. Table 8-1. I/O Configuration PxDIR PxREN PxOUT I/O Configuration Input Input with pulldown resistor Input with pullup resistor Output Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 295: I/O Function Selection
PxIE bit and the GIE bit are set. Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt. • Bit = 0: No interrupt is pending • Bit = 1: An interrupt is pending SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 296 ; Task starts here RETI ; Back to main program P1_1_HND ; Vector 4: Port 1 bit 1 ; Task starts here Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 297 Because port PJ is shared with the JTAG function, floating inputs may not be noticed when in an emulation environment. Port J is initialized to high-impedance inputs by default. SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 298 PxIFG flags. These flags can be used directly, or the corresponding PxIV register may be used. Note that the PxIFG flag cannot be cleared until the LOCKLPM5 bit has been cleared. Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 299 NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG flags are set, and it cannot be determined which port caused the I/O wakeup. SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 300 Port 1 Interrupt Enable Read/write Byte Section 8.4.13 or PAIE_L P1IFG Port 1 Interrupt Flag Read/write Byte Section 8.4.14 or PAIFG_L 300 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 301 Port 3 Interrupt Enable Read/write Byte Section 8.4.13 or PBIE_L P3IFG Port 3 Interrupt Flag Read/write Byte Section 8.4.14 or PBIFG_L SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 302 Port 5 Interrupt Enable Read/write Byte Section 8.4.13 or PCIE_L P5IFG Port 5 Interrupt Flag Read/write Byte Section 8.4.14 or PCIFG_L 302 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 303 Port 7 Interrupt Enable Read/write Byte Section 8.4.13 or PDIE_L P7IFG Port 7 Interrupt Flag Read/write Byte Section 8.4.14 or PDIFG_L SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 304 Port 9 Interrupt Enable Read/write Byte Section 8.4.13 or PEIE_L P9IFG Port 9 Interrupt Flag Read/write Byte Section 8.4.14 or PEIFG_L 304 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 305 Port 11 Interrupt Enable Read/write Byte Section 8.4.13 or PFIE_L P11IFG Port 11 Interrupt Flag Read/write Byte Section 8.4.14 or PFIFG_L SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 306 PAIE_L Read/write Byte PAIE_H Read/write Byte PAIFG Port A Interrupt Flag Read/write Word 0000h PAIFG_L Read/write Byte PAIFG_H Read/write Byte 306 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 307 0000h PBIE_L Read/write Byte PBIE_H Read/write Byte PBIFG Port B Interrupt Flag Read/write Word 0000h PBIFG_L Read/write Byte PBIFG_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 308 PCIE_L Read/write Byte PCIE_H Read/write Byte PCIFG Port C Interrupt Flag Read/write Word 0000h PCIFG_L Read/write Byte PCIFG_H Read/write Byte 308 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 309 0000h PDIE_L Read/write Byte PDIE_H Read/write Byte PDIFG Port D Interrupt Flag Read/write Word 0000h PDIFG_L Read/write Byte PDIFG_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 310 PEIE_L Read/write Byte PEIE_H Read/write Byte PEIFG Port E Interrupt Flag Read/write Word 0000h PEIFG_L Read/write Byte PEIFG_H Read/write Byte 310 Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 311 0000h PFIE_L Read/write Byte PFIE_H Read/write Byte PFIFG Port F Interrupt Flag Read/write Word 0000h PFIFG_L Read/write Byte PFIFG_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 312 0000h PJSEL1_L Read/write Byte PJSEL1_H Read/write Byte PJSELC Port J Complement Select Read/write Word 0000h PJSELC_L Read/write Byte PJSELC_H Read/write Byte Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 313: P1Iv Register
0Eh = Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG.6 10b = Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG.7; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 314: P3Iv Register
0Eh = Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG.6 10b = Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG.7; Interrupt Priority: Lowest Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 315: Pxin Register
Table 8-10. P1DIR Register Description Field Type Reset Description PxDIR Port x direction 0b = Port configured as input 1b = Port configured as output SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 316: Pxren Register
01b = Primary module function is selected 10b = Secondary module function is selected 11b = Tertiary module function is selected Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 317: Pxselc Register
Field Type Reset Description PxIE Port x interrupt enable 0b = Corresponding port interrupt disabled 1b = Corresponding port interrupt enabled SLAU272C – May 2011 – Revised November 2013 Digital I/O Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 318: Pxifg Register
Table 8-17. PxIFG Register Description Field Type Reset Description PxIFG Port x interrupt flag 0b = No interrupt is pending. 1b = Interrupt is pending. Digital I/O SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 319 Page ......... Cyclic Redundancy Check (CRC) Module Introduction ................CRC Standard and Bit Order ................CRC Checksum Generation ....................CRC Registers SLAU272C – May 2011 – Revised November 2013 CRC Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 320: Lfsr Implementation Of Crc-Ccitt Standard, Bit 0 Is The Msb Of The Result
MSB. The fact that bit 0 is treated for some as LSB, and for others as MSB, continues to cause confusion. The CRC16 module therefore provides a bit reversed register pair for CRC16 operations to support both conventions. CRC Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 321 If the checksum itself (with reversed bit order) is included into the CRC operation (as data written to CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero. SLAU272C – May 2011 – Revised November 2013 CRC Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 322: Implementation Of Crc-Ccitt Using The Crcdi And Crcinires Registers
The details of the implemented CRC algorithm are shown by the data sequences in Example 9-2 using word or byte accesses and the CRC data-in as well as the CRC data-in reverse byte registers. CRC Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 323 #039h, &CRCDIRB_L ; "9" #029B1h,&CRCINIRES ; compare result ; CRCRESR contains 08D94h &Success ; no error &Error ; to error handler SLAU272C – May 2011 – Revised November 2013 CRC Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 324: Crc Registers
Read/write Byte CRCINIRES_H Read/write Byte CRCRESR CRC Result Reverse Read only Word FFFFh Section 9.4.4 CRCRESR_L Read/write Byte CRCRESR_H Read/write Byte CRC Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 325: Crcdi Register
CRCINIRES and CRCRESR registers according to the CRC-CCITT standard. Reading the register returns the register CRCDI content. SLAU272C – May 2011 – Revised November 2013 CRC Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 326: Crcinires Register
CRC-CCITT standard). The order of bits is reverse (for example, CRCINIRES[15] = CRCRESR[0]) to the order of bits in the CRCINIRES register (see example code). CRC Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 327 The enhanced watchdog timer, WDT_A, is implemented in all devices..........................Topic Page ..................10.1 WDT_A Introduction .................... 10.2 WDT_A Operation .................... 10.3 WDT_A Registers SLAU272C – May 2011 – Revised November 2013 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 328 32-ms reset interval using the SMCLK. The user must set up or halt the WDT_A before the initial reset interval expires. Watchdog Timer (WDT_A) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 329: Watchdog Timer Block Diagram
WDTIS2 WDTIS1 WDTIS0 X_CLK request Clock SMCLK request Request ACLK request Logic VLOCLK request Figure 10-1. Watchdog Timer Block Diagram SLAU272C – May 2011 – Revised November 2013 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 330 In interval timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced, or can be reset with software. Watchdog Timer (WDT_A) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 331 ; Change watchdog timer interval MOV #WDTPW+WDTCNTCL+SSEL,&WDTCTL ; Stop the watchdog MOV #WDTPW+WDTHOLD,&WDTCTL ; Change WDT to interval timer mode, clock/8192 interval MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS2+WDTIS0,&WDTCTL SLAU272C – May 2011 – Revised November 2013 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 332 Register Name Type Access Reset Section WDTCTL Watchdog Timer Control Read/write Word 6904h Section 10.3.1 WDTCTL_L Read/write Byte WDTCTL_H Read/write Byte Watchdog Timer (WDT_A) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 333: Wdtctl Register
110b = Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) 111b = Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) SLAU272C – May 2011 – Revised November 2013 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 334: Timer_A Registers
(see the device-specific data sheet). This chapter describes the operation and use of the Timer_A module..........................Topic Page ..................11.1 Timer_A Introduction ................... 11.2 Timer_A Operation ................... 11.3 Timer_A Registers Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 335 = 0. The suffix n, where n = 0 to 6, represents the specific capture/compare registers associated with the Timer_A instantiation. SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 336: Timer_A Block Diagram
EQU6 SCCI Set TAxCCR6 CCIFG Output D Set Q OUT6 Signal Unit4 EQU0 Timer Clock Reset OUTMOD Figure 11-1. Timer_A Block Diagram Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 337 TAxCCR0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 338: Up Mode
However, one additional count may occur before the counter rolls to zero. Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 339: Continuous Mode
TAxCCR1b TAxCCR1c TAxCCR0d TAxCCR0b TAxCCR0c 0FFFFh TAxCCR1a TAxCCR1d TAxCCR0a Figure 11-6. Continuous Mode Time Intervals SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 340: Up/Down Mode
When the timer is counting in the up direction and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 341: Output Unit In Up/Down Mode
Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 11-10). SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 342: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TAxCCTLn Second Capture Idle Taken COV = 1 Figure 11-11. Capture Cycle Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 343: Output Modes
The output is reset when the timer counts to the TAxCCRn value. It is set when the timer counts to the TAxCCR0 value. SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 344: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TAIFG TAIFG TAIFG Figure 11-12. Output Example – Timer in Up Mode Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 345: Output Example - Timer In Continuous Mode
Output Mode 6: oggle/Set Output Mode 7: Reset/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events Figure 11-13. Output Example – Timer in Continuous Mode SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 346: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TA0CCTL1 ; Set output mode=7 #OUTMOD,&TA0CCTL1 ; Clear unwanted bits Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 347 TAxIV register, TAxCCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TAxCCR2 CCIFG flag generates another interrupt. SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 348 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TA0CCR1 ; Task starts here RETI ; Back to main program Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 349 0000h Section 11.3.4 TAxIV Timer_Ax Interrupt Vector Read only Word 0000h Section 11.3.5 TAxEX0 Timer_Ax Expansion 0 Read/write Word 0000h Section 11.3.6 SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 350: Taxctl Register
Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled TAIFG Timer_A interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 351: Taxr Register
Table 11-5. TAxR Register Description Field Type Reset Description 15-0 TAxR Timer_A register. The TAxR register is the count of Timer_A. SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 352: Taxcctln Register
Output. For output mode 0, this bit directly controls the state of the output. 0b = Output low 1b = Output high Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 353: Capture/Compare Interrupt Flag
0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 354: Taxccrn Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest Timer_A SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 355: Taxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 SLAU272C – May 2011 – Revised November 2013 Timer_A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 356: Timer_B Registers
(see the device-specific data sheet). This chapter describes the operaand use of the Timer_B module..........................Topic Page ..................12.1 Timer_B Introduction ................... 12.2 Timer_B Operation ................... 12.3 Timer_B Registers Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 357 Timer_B TBxCCRn registers are double-buffered and can be grouped. • All Timer_B outputs can be put into a high-impedance state. • The SCCI bit function is not implemented in Timer_B. SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 358: Timer_B Block Diagram
UP/DOWN CCR1 Set TBxCCR6 CCIFG Output D Set Q OUT6 Signal Unit6 EQU0 Timer Clock Reset OUTMOD Figure 12-1. Timer_B Block Diagram Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 359 TBxCL0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 360: Up Mode Flag Setting
If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 361: Continuous Mode
TBxCL1b TBxCL1c TBxCL0d TBxCL0b TBxCL0c TBxR (max) TBxCL1a TBxCL1d TBxCL0a EQU0 Interrupt EQU1 Interrupt Figure 12-6. Continuous Mode Time Intervals SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 362: Up/Down Mode
TBxCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero. Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 363: Output Unit In Up/Down Mode
The input signal level can be read at any time via the CCI bit. Devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals. SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 364: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TBxCCTLn Second Capture Idle Taken COV = 1 Figure 12-11. Capture Cycle Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 365: Tbxcln Load Events
TBxCCRn to TBxCLn when TBxR counts to the old TBxCL0 value or to 0 for up/down mode. New data is transferred from TBxCCRn to TBxCLn when TBxR counts to the old TBxCLn value. SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 366: Mode
The output is reset when the timer counts to the TBxCLn value. It is set when the timer Reset/Set counts to the TBxCL0 value. 366 Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 367: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TBIFG TBIFG TBIFG Figure 12-12. Output Example – Timer in Up Mode SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 368: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set Interrupt Events TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Figure 12-13. Output Example – Timer in Continuous Mode Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 369: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TBCCTLx ; Set output mode=7 #OUTMOD,&TBCCTLx ; Clear unwanted bits SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 370: Capture/Compare Tbxccr0 Interrupt Flag
The latencies are: • Capture/compare block CCR0: 11 cycles • Capture/compare blocks CCR1 to CCR6: 16 cycles • Timer overflow TBIFG: 14 cycles Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 371 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TB0CCR1 ; Task starts here RETI ; Back to main program SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 372 0000h Section 12.3.4 TBxIV Timer_B Interrupt Vector Read only Word 0000h Section 12.3.5 TBxEX0 Timer_B Expansion 0 Read/write Word 0000h Section 12.3.6 Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 373: Tbxctl Register
The TBCLR bit is automatically reset and is always read as zero. TBIE Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 374 Table 12-6. TBxCTL Register Description (continued) Field Type Reset Description TBIFG Timer_B interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 375: Tbxr Register
Table 12-7. TBxR Register Description Field Type Reset Description 15-0 TBxR Timer_B register. The TBxR register is the count of Timer_B. SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 376: Tbxcctln Register
CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled Undef Capture/compare input. The selected input signal can be read by this bit. Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 377 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 378: Tbxccrn Register
Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBxCCRn register when a capture is performed. Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 379: Tbxiv Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Timer_B Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 380: Tbxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 Timer_B SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 381 This chapter describes the RTC_B module..........................Topic Page ..............13.1 Real-Time Clock RTC_B Introduction ..................... 13.2 RTC_B Operation ..................... 13.3 RTC_B Registers SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 382 Real-time clock initialization Most RTC_B module registers have no initial condition. These registers must be configured by user software before use. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 383: Rtc_B Block Diagram
Calendar RTCYEARH RTCYEARL RTCMON RTCDAY Set_RTCAIFG Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Figure 13-1. RTC_B Block Diagram SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 384 RTCAIE, RTCAIFG, and AE bits prior to writing initial or new time values to the RTC time registers. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 385 In addition, all flags can be cleared via software. SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 386 ; Vector 6: RTCAIFG Flag ; Task starts here RETI ; Back to main program RT0PSIFG_HND ; Vector 8: RT0PSIFG Flag Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 388 If a fault occurs during LPMx.5 and the RTCOFIE was set before entering LPMx.5, a wake-up event is issued. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 389 Real-Time Clock Hour Read/write Byte undefined retained or RTCTIM1_L RTCDOW Real-Time Clock Day of Week Read/write Byte undefined retained or RTCTIM1_H SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 390: Rtc_B Registers
BCD2BIN BCD-to-Binary Conversion Register Read/write Word not retained Do not access the RTCYEAR register in byte mode. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 391: Rtcctl0 Register
Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 392: Rtcctl1 Register
00b = Minute changed 01b = Hour changed 10b = Every day at midnight (00:00) 11b = Every day at noon (12:00) Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 393: Rtcctl2 Register
00b = No frequency output to RTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 394: Rtcsec Register
Seconds – high digit. Valid values are 0 to 5. Seconds – low digit undefined Seconds – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 395: Rtcmin Register
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 396: Rtchour Register
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 397: Rtcdow Register
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 398: Rtcmon Register
Month – high digit. Valid values are 0 or 1. Month – low digit undefined Month – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 399: Rtcyear Register
Decade. Valid values are 0 to 9. Year – lowest digit undefined Year – lowest digit. Valid values are 0 to 9. SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 400: Rtcamin Register
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 401: Rtcahour Register
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 402: Rtcadow Register
1b = This alarm register is disabled Always reads as 0. Day of week undefined Day of week. Valid values are 0 to 6. Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 403: Rtcaday Register
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 404: Rtcps0Ctl Register
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 405: Rtcps1Ctl Register
Prescale timer 1 interrupt flag. In modules supporting LPMx.5 this interrupt can be used as LPMx.5 wake-up event. 0b = No time event occurred 1b = Time event occurred SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 406: Rtcps0 Register
Figure 13-29. RTCPS1 Register RT1PS Table 13-29. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 407: Rtciv Register
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0Ch = Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG 0Eh = Reserved; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 408: Bin2Bcd Register
15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number Write: 16-bit BCD number to be converted Real-Time Clock B (RTC_B) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 409 ........................... Topic Page ..........14.1 32-Bit Hardware Multiplier (MPY32) Introduction ..................... 14.2 MPY32 Operation ..................... 14.3 MPY32 Registers SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 410 8-bit and 24-bit multiplications without requiring a "sign extend" instruction The MPY32 block diagram is shown in Figure 14-1. 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 411: Mpy32 Block Diagram
MPYSAT 32-bit Adder MPYFRAC MPYC 32-bit Demultiplexer SUMEXT RES3 RES2 RES1/RESHI RES0/RESLO 32-bit Multiplexer Figure 14-1. MPY32 Block Diagram SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 412: Result Availability (Mpyfrac = 0, Mpysat = 0)
24/32 × 8/16 OP2 written 8/16 × 24/32 OP2L written OP2H written 24/32 × 24/32 OP2L written OP2H written 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 413: Op1 Registers
During the execution of the 16-bit operation, the content of the high-word is ignored. SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 414: Sumext And Mpyc Contents
00000h Result was positive or zero No carry for result 0FFFFh Result was negative Result has a carry 414 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 415 ; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&MPYS_B ; Load 1st operand MOV.B #034h,&OP2_B ; Load 2nd operand ; Process results SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 416: Q15 Format Representation
In fractional mode, the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for 16×16-bit operations and bits 64 and 65 for 32×32-bit operations – not only bits 32 or 64, respectively. 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 417: Result Availability In Fractional Mode (Mpyfrac = 1, Mpysat = 0)
&K2,&OP2 ; Load K2 to get A2*K2 &RES1,&PROD ; Save A1*K1+A2*K2 as result #MPYSAT+MPYFRAC,&MPY32CTL0 ; turn back to normal SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 418: Saturation Flow Chart
14=0 RES0 = 00000h RES0 = 00000h 32-bit Saturation 64-bit Saturation completed completed Figure 14-4. Saturation Flow Chart 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 419 14.2.5 Putting It All Together Figure 14-5 shows the complete multiplication flow, depending on the various selectable modes for the MPY32 module. SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 420: Multiplication Flow Chart
MPYC and bit15 of unshifted RES1. unshifted RES3. MPYSAT=1 MPYSAT=1 32-bit Saturation 64-bit Saturation Multiplication completed Figure 14-5. Multiplication Flow Chart 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 421 08000 0000h. Adding a negative number to it would again cause an underflow, thus, the final result is also saturated to 08000 0000h. SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 422 ; Interrupts may be enabled before ; processing results if result ; registers are stored and restored in ; interrupt service routines 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 423 DMA. The signal into the DMA controller is 'Multiplier ready' (see the DMA Controller chapter for details). SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 424: Mpy32 Registers
24-bit operand 1 – signed multiply – high byte Read/write Byte Undefined MAC32L 32-bit operand 1 – multiply accumulate – low word Read/write Word Undefined 424 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 425: Alternative Registers
8-bit operand one – signed multiply accumulate MACS_B or MACS_L MACS32L_B or MACS32L_L 16x16-bit result low word RESLO RES0 16x16-bit result high word RESHI RES1 SLAU272C – May 2011 – Revised November 2013 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 426: Mpy32Ctl0 Register
It is used to restore the SUMEXT content in MAC mode. 0b = No carry for result 1b = Result has a carry 32-Bit Hardware Multiplier (MPY32) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 427 This chapter describes the REF module..........................Topic Page ..................... 15.1 REF Introduction ..................15.2 Principle of Operation ....................15.3 REF Registers SLAU272C – May 2011 – Revised November 2013 REF Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 428: Ref Block Diagram
BANDGAP Vref Local − Buffer Switch COMP_E0 Local Buffer 1.5/2.0/2.5V COMP_E1 Local REFGENREQ Buffer REFBGREQ REFMODEREQ Figure 15-1. REF Block Diagram REF Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 429: Ref Control Of Reference System (Refmstr = 1) (Default)
REFGEN subsystem is enabled. After the specified settling time, the variable reference line voltage is stable and ready for use. The REFVSEL settings determine which voltage is generated on the variable reference line. SLAU272C – May 2011 – Revised November 2013 REF Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 430 For devices that contain an ADC10_B module, if the ADC is not sampling or converting but the REFON bit is set the REF module remains on. REF Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 431: Ref Registers
Offset Acronym Register Name Type Access Reset Section REFCTL0 REFCTL0 Read/write Word 0000h Section 15.3.1 REFCTL0_L Read/write Byte REFCTL0_H Read/write Byte SLAU272C – May 2011 – Revised November 2013 REF Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 432: Refctl0 Register
Can be modified only when REFGENBUSY = 0. 0b = Disables reference if no other reference requests are pending 1b = Enables reference REF Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 433 ADC10_B module..........................Topic Page ..................16.1 ADC10_B Introduction ..................16.2 ADC10_B Operation ..................16.3 ADC10_B Registers SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 434 Figure 16-1 shows the block diagram of ADC10_B. The on-chip generation is located in the reference module (see the device-specific data sheet). ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 435: Adc10_B Block Diagram
MODCLK is sourced from the MODOSC in the CS module. See the CS chapter for more information. When using ADC10SHP = 0, no synchronisation of the trigger input is done. Figure 16-1. ADC10_B Block Diagram SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 436: Analog Multiplexer
These transients decay and settle before causing errant conversion. R ~ 100 ADC10MCTL0.0–3 Input ESD Protection Figure 16-2. Analog Multiplexer ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 437 When SAMPCON is high, sampling is active. The high- sample. to-low SAMPCON transition starts the conversion after synchronization with ADC10CLK (see Figure 16-3). SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 438: Extended Sample Mode
Start Stop Start Conversion Sampling Sampling Conversion Complete 12 × ADC10CLK SAMPCON sample convert sync ADC10CLK Figure 16-4. Pulse Sample Mode ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 439: Analog Input Equivalent Circuit
A sequence of channels is converted once. Repeat-single-channel A single channel is converted repeatedly. Repeat-sequence-of-channels A sequence of channels is converted repeatedly. SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 440: Single-Channel Single-Conversion Mode
ADC10INCHx All bit- or registernames are marked with bold font, signals are noted in normal font Figure 16-6. Single-Channel Single-Conversion Mode ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 441: Sequence-Of-Channels Mode
- input channel Ax All bit- or registernames are marked with bold font, signals are noted in normal font Figure 16-7. Sequence-of-Channels Mode SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 442: Repeat-Single-Channel Mode
- pointer to the selected ADC10_A channel defined by ADC10INCHx All bit- or registernames are marked with bold font, signals are noted in normal font Figure 16-8. Repeat-Single-Channel Mode ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 443: Repeat-Sequence-Of-Channels Mode
- input channel Ax All bit- or registernames are marked with bold font, signals are noted in normal font Figure 16-9. Repeat-Sequence-of-Channels Mode SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 444 ADC10MEM0. This update is only a set of the corresponding interrupt flag. When using the window comparator flags, make sure that they are reset by software according to the application needs. ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 445: Typical Temperature Sensor Transfer Function
(see the device-specific data sheet for parameters). 1050 1000 Ambient Temperature - Degrees Celsius Figure 16-10. Typical Temperature Sensor Transfer Function SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 446: Adc10_B Grounding And Noise Considerations
10 F µ 100 nF Analog Power Supply Decoupling 10 F µ 100 nF Figure 16-11. ADC10_B Grounding and Noise Considerations ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 447 (ADC10OV interrupt condition) is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC10HIIFG generates another interrupt. SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 448 ; Handle window comparator low Interrupt RETI ; Return ; ADIN ; Handle window comparator in window Interrupt RETI ; Return ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 449: Adc10_B Registers
0000h Section 16.3.11 ADC10IFG ADC10_B Interrupt Flag register Read/write 0000h Section 16.3.12 ADC10IV ADC10_B Interrupt Vector register Read/write 0000h Section 16.3.13 SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 450: Adc10Ctl0 Register
0b = ADC10_B off 1b = ADC10_B on Reserved Reserved. Always reads as 0. ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 451 ADC10SC and ADC10ENC may be set together with one instruction. ADC10SC is reset automatically. 0b = No sample-and-conversion-start 1b = Start sample-and-conversion SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 452: Adc10Ctl1 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 453: Adc10Ctl1 Register Description
ADC10_B busy. This bit indicates an active sample or conversion operation. 0b = No operation is active. 1b = A sequence, sample, or conversion is active. SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 454: Adc10Ctl2 Register
1b = ADC10_B buffer supports up to approximately 50 ksps. Reserved Reserved. Always reads as 0. Reserved Reserved. Must be written as 0. ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 455: Adc10Mem0 Register
2s-complement format during read back. Writing to the conversion memory register corrupts the results. SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 456: Adc10Mctl0 Register
1010b = Temperature diode from REF module 1011b = (AVCC – AVSS) / 2 1100b = A12 1101b = A13 1110b = A14 1111b = A15 ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 457: Adc10Hi Register
Bit 15 is the MSB. Bits 5–0 are 0 in 10-bit mode, and bits 7–0 are 0 in 8- bit mode. This data format is used if ADC10DF = 1. SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 458: Adc10Lo Register
Bit 15 is the MSB. Bits 5–0 are 0 in 10-bit mode, and bits 7–0 are 0 in 8- bit mode. This data format is used if ADC10DF = 1. ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 459: Adc10Ie Register
Interrupt enable. This bits enable or disable the interrupt request for a completed ADC10_B conversion. 0b = Interrupt disabled 1b = Interrupt enabled SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 460: Adc10Ifg Register
ADC10MEM0 get read, or it may be reset by software. 0b = No interrupt pending 1b = Interrupt pending ADC10_B Module SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 461: Adc10Iv Register
0Ah = Interrupt Source: ADC10IN Interrupt flag; Interrupt Flag: ADC10INIFG 0Ch = Interrupt Source: ADC10_B memory Interrupt flag; Interrupt Flag: ADC10IFG0; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 462: Comparator_D Registers
Comparator_D supports general comparator functionality for up to 16 channels..........................Topic Page ................17.1 Comparator_D Introduction .................. 17.2 Comparator_D Operation .................. 17.3 Comparator_D Registers Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 463: Comparator_D Block Diagram
CDREF1 CDREF0 CDRS CDOUTPOL 0001 Reference Voltage from shared Generator reference CD12 CD13 CD14 1110 CD15 1111 Figure 17-1. Comparator_D Block Diagram SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 464 The CDSHORT bit shorts the Comparator_D inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 17-2. Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 465: Comparator_D Sample-And-Hold
Selecting the output filter can reduce errors associated with comparator oscillation. SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 466: Rc-Filter Response At The Output Of The Comparator
CDOUT is 1 and Vref0 is used while CDOUT is 0. This allows the generation of a hysteresis without using external components. Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 467: Transfer Characteristic And Power Dissipation In A Cmos Inverter/Buffer
6. A reference resister Rref is compared to Rmeas. Rref Px.x Rmeas Px.y Capture Input Of a Timer 0.25 × V Figure 17-6. Temperature Measurement System SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 468: Timing For Temperature Measurement Systems
–R × C × ln meas meas ref1 –R × C × ln meas meas meas = R × meas Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 469 Comparator_D control register 3 Read/write 0000h Section 17.3.4 CDINT Comparator_D interrupt register Read/write 0000h Section 17.3.5 CDIV Comparator_D interrupt vector word Read 0000h Section 17.3.6 SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 470: Cdctl0 Register
Reserved Reserved. Always reads as 0. CDIPSEL Channel input selected for the V+ terminal of the comparator if CDIPEN is set to Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 471: Cdctl1 Register
CDOUT Output value. This bit reflects the value of the Comparator_D output. Writing this bit has no effect on the comparator output. SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 472: Cdctl2 Register
1b = V(REF) is applied to the + terminal CDREF0 Reference resistor tap 0. This register defines the tap of the resistor string while CDOUT = 0. Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 473: Cdctl3 Register
Comparator_D. The bit CDPDx disabled the port of the comparator channel x. 0b = The input buffer is enabled 1b = The input buffer is disabled SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 474: Cdint Register
Comparator_D output interrupt flag. The bit CDIES defines the transition of the output setting this bit. 0b = No interrupt pending 1b = Output interrupt pending Comparator_D SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 475: Cdiv Register
02h = Interrupt Source: CDOUT interrupt; Interrupt Flag: CDIFG; Interrupt Priority: Highest 04h = Interrupt Source: CDOUT interrupt inverted polarity; Interrupt Flag: CDIIFG; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Comparator_D Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 476 Introduction – UART Mode ..............18.3 eUSCI_A Operation – UART Mode ................. 18.4 eUSCI_A UART Registers Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 477 Independent interrupt capability for receive, transmit, start bit received, and transmit complete Figure 18-1 shows the eUSCI_Ax when configured for UART mode. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 478: Eusci_Ax Block Diagram - Uart Mode (Ucsync = 0)
UCTXADDR UCMODEx UCSPB Figure 18-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 479: Character Format
When an idle line is detected, the UCIDLE bit is set. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 480: Idle-Line Format
The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data is misinterpreted as an address. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 481: Address-Bit Multiprocessor Format
(UCTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 482: Auto Baud-Rate Detection - Break/Synch Sequence
The latter case can be discovered by checking the received data and the UCFE bit. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 483: Uart Vs Irda Data Format
= Wake time from any low-power mode. Zero when the device is in active mode. WAKE SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 484: Receive Error Conditions
UCAxRXBUF to detect this condition. Note that, in this case, the UCRXERR flag is not set. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 485: Glitch Suppression, Eusci_A Receive Not Started
If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud-rate generator is turned off. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 486: Bitclk Baud-Rate Timing With Ucos16
Bit 6 Bit 7 (Start Bit) 0x00 0x01 ⋮ 0x35 0x36 0x37 ⋮ 0xff 486 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 487: Bitclk16 Modulation Pattern
Table 18-3. BITCLK16 Modulation Pattern Number of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 488: Brclk /Baudrate
However it is also possible to look up the correct settings in table with typical crystals (see Table 18-5). Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 489 –0.5 BRCLKs and +0.5 RCLKs, independent of the selected baud- SYNC rate generation mode. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 490: Receive Error
(see the device-specific data sheet). Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 491: Recommended Settings For Typical Crystals And Baudrates
0x92 -1.62 1.37 -3.56 2.06 8388608 460800 0x11 3.37 -5.31 5.55 12000000 9600 0.04 SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 492 UCTXIFG is set after a PUC or when UCSWRST = 1. UCTXIE is reset after a PUC or when UCSWRST = 1. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 493: Uart State Change Interrupt Flags
// Vector 6: UCSTTIFG break; case 0x08: ... // Vector 8: UCTXCPTIFG break; default: break; SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 494: Eusci_A Uart Registers
It is recommended to access these registers using 16-bit access. If 8-bit access is used, the corresponding bit names must be followed by "_H". Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 495: Ucaxctlw0 Register
0b = Received break characters do not set UCRXIFG. 1b = Received break characters set UCRXIFG. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 496: Ucaxctlw1 Register
01b = Approximately 50 ns 10b = Approximately 100 ns 11b = Approximately 200 ns Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 497: Ucaxbrw Register
Baud-Rate Generation" section shows the modulation pattern. Reserved Reserved UCOS16 Oversampling mode enabled 0b = Disabled 1b = Enabled SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 498: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI_A inactive 1b = eUSCI_A transmitting or receiving Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 499: Ucaxrxbuf Register
UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 500: Ucaxabctl Register
1b = Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 501: Ucaxirctl Register
UCIREN IrDA encoder/decoder enable 0b = IrDA encoder/decoder disabled 1b = IrDA encoder/decoder enabled SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 502: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 503: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCAxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 504: Ucaxiv Register
06h = Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 08h = Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 505 Operation – SPI Mode ..................19.4 eUSCI_A SPI Registers ..................19.5 eUSCI_B SPI Registers SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 506 Slave operation in LPM4 Figure 19-1 shows the eUSCI when configured for SPI mode. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 507: Eusci Block Diagram - Spi Mode
Set UCFE Transmit State Machine Set UCxTXIFG Figure 19-1. eUSCI Block Diagram – SPI Mode SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 508: Ucxste Operation
Configure ports. Clear UCSWRST via software. BIC.B #UCSWRST,&UCxCTL1 Enable interrupts (optional) via UCRXIE or UCTXIE. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 509: Eusci Master And External Slave (Ucstem = 0)
The fourth pin is used as output to generate a slave enable signal (UCSTEM = 1). The bit UCSTEM is used to select the corresponding mode. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 510: Eusci Slave And External Master
UCxRXBUF before new data is moved to UCxRXBUF. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 511 The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the eUSCI. Timing for each case is shown in Figure 19-4. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 512: Eusci Spi Timing With Ucmsb
Data written to UCxTXBUF when UCTXIFG = 0 may result in erroneous data transmission. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 513 RETI ; Return RXIFG_ISR ; Vector 2 ; Task starts here RETI ; Return SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 514: Eusci_A Spi Registers
Interrupt Flag Read/write Word Section 19.4.7 UCAxIV eUSCI_Ax Interrupt Vector Read Word 0000h Section 19.4.8 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 515: Ucaxctlw0 Register
1b = STE pin is used to generate the enable signal for a 4-wire slave SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 516 0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 517: Ucaxbrw Register
Table 19-4. UCAxBRW Register Description Field Type Reset Description 15-0 UCBRx Bit clock prescaler setting. /(UCBRx+1) BitClock BRCLK SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 518: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 519: Ucaxrxbuf Register
UCRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 520: Ucaxtxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 521: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 522: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 523: Ucaxiv Register Description
Priority: Highest 004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 524: Ucaxiv Register 19.5 Eusci_B Spi Registers
Interrupt Flag Read/write Word Section 19.5.7 UCBxIV eUSCI_Bx Interrupt Vector Read Word 0000h Section 19.5.8 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 525: Ucbxctlw0 Register
1b = STE pin is used to generate the enable signal for a 4-wire slave SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 526: Ucbxctlw0 Register Description
0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 527: Ucbxbrw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 528: Ucbxrxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 529: Ucbxie Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 530: Ucbxiv Register
Priority: Highest 0004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 531: Enhanced Universal Serial Communication Interface (Eusci) - I 2 C Mode
................20.3 eUSCI_B Operation – I C Mode ..................20.4 eUSCI_B I2C Registers SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 532: Enhanced Universal Serial Communication Interface B (Eusci_B) Overview
Slave receiver START detection for auto wake-up from LPMx modes (not LPM3.5 and LPM4.5) Figure 20-1 shows the eUSCI_B when configured in I C mode. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 533: Mode
SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 534: Eusci_B Initialization And Reset
SCL clock. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 535: Addressing Modes
10-bit addressing mode with the eUSCI_B module. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 536: I 2 C Quick Setup
The recommended structure of the interrupt service routine can be found in Example 20-3. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 537: Module Operating Modes
SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 538: Time-Line Legend
C state machine returns to its address-reception state. Figure 20-9 shows the slave transmitter operation. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 539: C Slave Receiver Mode
To avoid loss of data, the UCBxRXBUF must be read before UCTXNACK is set. When the master generates a STOP condition, the UCSTPIFG flag is set. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 540: C Slave 10-Bit Addressing Mode
R/W bit set. This sets the UCSTTIFG flag if it was previously cleared by software, and the eUSCI_B modules switches to transmitter mode with UCTR = 1. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 541 SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 542: C Master Transmitter Mode
START, it must be written into UCBxTXBUF again. Any set UCTXSTT or UCTXSTP is also discarded. Figure 20-12 shows the I C master transmitter operation. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 543 (UCGC=1 if general call) USCI continues as Slave Receiver Figure 20-12. I C Master Transmitter Mode SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 544: I 2 C Master Receiver Mode
C transaction is initiated with setting UCTXSTT = 1. Otherwise, the current transaction might be affected. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 545 UCTXIFG=1 USCI continues as Slave Transmitter Figure 20-13. I C Master Receiver Mode SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 546: Arbitration Procedure Between Two Master Transmitters
Master 1 sends a repeated START condition and master 2 sends a STOP condition. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 547: Glitch Filtering
• eUSCI_B is acting as master and a connected slave drives SCL low. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 548: C Clock Generation And Synchronization 20.3.8 Byte Counter
UCBCNT interrupt routine is executed in time to generate for example a RESTART. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 549: Multiple Slave Addresses
SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 550: Eusci_B Interrupts In I C Mode
C State Change Interrupt Operation Table 20-2 describes the I C state change interrupt flags. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 551 UCBxIV. The UCBxIV value is added to the PC to automatically jump to the appropriate routine. The example is given for eUSCI0_B. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 552 0x1c: ... // Vector 28: clock low timeout break; case 0x1e: ... // Vector 30: 9th bit break; default: break; SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 553: Eusci_B I2C Registers
Word 0002h Section 20.4.16 UCBxIV eUSCI_Bx Interrupt Vector Read Word 0000h Section 20.4.17 SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 554: Ucbxctlw0 Register
0b = Do not acknowledge the slave address 1b = Acknowledge the slave address SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 555 0b = Disabled. eUSCI_B released for operation. 1b = Enabled. eUSCI_B logic held in reset state. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 556: Ucbxctlw1 Register
UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold. 11b = Reserved SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 557 00b = 50 ns 01b = 25 ns 10b = 12.5 ns 11b = 6.25 ns SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 558: Ucbxbrw Register
UCBBUSY Bus busy 0b = Bus inactive 1b = Bus busy Reserved Reserved SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 559: Ucbxtbcnt Register
UCASTPx is different from 00. Modify only when UCSWRST = 1. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 560: Ucbxrxbuf Register
Writing to the transmit data buffer clears the UCTXIFGx flags. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 561: Ucbxi2Coa0 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 562: Ucbxi2Coa1 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 563: Ucbxi2Coa3 Register
SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 564: Ucbxaddmask Register
MSB and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB. SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 565: Ucbxie Register
UCSTPIE STOP condition interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 566 UCRXIE0 Receive interrupt enable 0 0b = Interrupt disabled 1b = Interrupt enabled SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 567: Ucbxifg Register
(see the Byte Counter Interrupt section). 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 568 UCBxI2COA0 was on the bus in the same frame. 0b = No interrupt pending 1b = Interrupt pending SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 569: Ucbxiv Register
1Ch = Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 1Eh = Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest SLAU272C – May 2011 – Revised November 2013 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 570: Embedded Emulation Module (Eem)
........................... Topic Page ..........21.1 Embedded Emulation Module (EEM) Introduction ..................21.2 EEM Building Blocks ..................21.3 EEM Configurations Embedded Emulation Module (EEM) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 571: Embedded Emulation Module (Eem) Introduction
MSP430 devices have the same or a similar feature set. For details, see the user's guide of the applicable debugger. SLAU272C – May 2011 – Revised November 2013 Embedded Emulation Module (EEM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 572: Large Implementation Of Eem
& & & Trigger Sequencer CPU Stop Start/Stop State Storage Start/Stop Cycle Counter Figure 21-1. Large Implementation of EEM Embedded Emulation Module (EEM) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 573: Eem Building Blocks
On some devices, the cycle counter operation can be controlled using triggers. This allows, for example, conditional profiling, such as profiling a specific section of code. SLAU272C – May 2011 – Revised November 2013 Embedded Emulation Module (EEM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 574: Clock Control
Hardware breakpoints using the CPU stop reaction • At least one 40-bit cycle counter • Enhanced clock control with individual control of module clocks Embedded Emulation Module (EEM) SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 575: Revision History
Added PJSELC register. Section 11.2.1.1 Added INCLK as a clock source option. Section 11.3.1 Changed TASSEL bit option 11b to INCLK. SLAU272C – May 2011 – Revised November 2013 Revision History Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 576 Added note regarding clearing of any pending port interrupt flags prior to LPMx.5 entry. Section 8.3.3 Added requirement that LOCKLPM5 must be cleared (if set) to re-enter LPM5 mode. Revision History SLAU272C – May 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 577 Update slave receiver figures to include clearing of STP bit on general calls. 20.3.5.1.2 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SLAU272C – May 2011 – Revised November 2013 Revision History Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 578 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

Texas Instruments MSP430FR57 Series User Manual

Msp430Fr57Xx Family User's Guide

Preface

1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)

2 Power Management Module and Supply Voltage Supervisor

3 Clock System (CS)

4 Cpux

5 FRAM Controller (FRCTL)

6 Memory Protection Unit (MPU)

7 DMA Controller

Enhanced Universal Serial Communication Interface (Eusci) - I 2 C Mode

Embedded Emulation Module (EEM)

Revision History

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Summary of Contents for Texas Instruments MSP430FR57 Series