Related Manuals for Texas Instruments MSP430FR58 Series
Summary of Contents for Texas Instruments MSP430FR58 Series
- Page 1 MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide Literature Number: SLAU367P October 2012 – Revised April 2020...
- Page 2 1.15.3 SFRRPCR Register ......................1.16 SYS Registers ....................1.16.1 SYSCTL Register ....................1.16.2 SYSJMBC Register ....................1.16.3 SYSJMBI0 Register ....................1.16.4 SYSJMBI1 Register Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 3 Constant Generator Registers (CG1 and CG2) ..............4.3.5 General-Purpose Registers (R4 to R15) ......................Addressing Modes ....................4.4.1 Register Mode ....................4.4.2 Indexed Mode SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 4 FRAM Controller A (FRCTL_A) Introduction ................FRAM Controller A (FRCTL_A) Operation ..................8.2.1 FRCTL_A Error Detection ................ 8.2.2 Programming FRAM Memory Devices ....................8.2.3 Access Control Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 5 11.2.8 Using DMA With System Interrupts ..................11.2.9 DMA Controller Interrupts ..........11.2.10 Using the eUSCI_B I C Module With the DMA Controller SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 6 14.2.3 Read the Data (128-Bit State) ................. 14.2.4 Trigger an Encryption or Decryption ....................... 14.2.5 Encryption ....................... 14.2.6 Decryption ..................14.2.7 Decryption Key Generation Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 7 USS Power States ................ 19.4 Interface to the ASQ (Acquisition Sequencer) ..................19.4.1 Start New Measurements ..............19.4.2 Stop Measurement Before Completion SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 8 21.2.6 Excitation Pulse Frequency on PPG or PPG_A ............... 21.2.7 Extra Excitation Pulse Frequency on PPG_A ..................21.2.8 Test Tone Generation ..................21.3 Physical Interface (PHY) Block Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 9 21.8.38 SAPHATM_B/SAPH_AATM_B Register (Offset = 70h) [reset = 0h] ........21.8.39 SAPHATM_C/SAPH_AATM_C Register (Offset = 72h) [reset = 0h] ........21.8.40 SAPHATM_D/SAPH_AATM_D Register (Offset = 74h) [reset = 0h] SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 10 23.2.3 Setting the Pulse Rate ..................23.2.4 Reading Pulse Counter ............. 23.2.5 Synchronizing Pulse Generator Timing to Application ..............23.2.6 Various Resets During MTIF Operation Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 11 26.2.3 Timer Mode Control ..................26.2.4 Capture/Compare Blocks ...................... 26.2.5 Output Unit ....................26.2.6 Timer_B Interrupts ......................26.3 Timer_B Registers ....................26.3.1 TBxCTL Register SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 12 28.3.31 BCD2BIN Register ....................Real-Time Clock C (RTC_C) ................29.1 Real-Time Clock (RTC_C) Introduction ......................29.2 RTC_C Operation ....................29.2.1 Calendar Mode Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 13 29.4.38 RTCSECBAKx Register – Hexadecimal Format ..............29.4.39 RTCSECBAKx Register – BCD Format ............29.4.40 RTCMINBAKx Register – Hexadecimal Format ..............29.4.41 RTCMINBAKx Register – BCD Format SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 14 ................31.3.1 eUSCI Initialization and Reset ....................31.3.2 Character Format ....................31.3.3 Master Mode ...................... 31.3.4 Slave Mode ....................... 31.3.5 SPI Enable Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 15 32.4.11 UCBxI2COA3 Register ..................32.4.12 UCBxADDRX Register ................... 32.4.13 UCBxADDMASK Register ..................32.4.14 UCBxI2CSA Register ....................32.4.15 UCBxIE Register .................... 32.4.16 UCBxIFG Register SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 16 35.2.6 Reference Voltage Generator ................35.2.7 Port Disable Register (CEPD) ..................35.2.8 Comparator_E Interrupts ............. 35.2.9 Comparator_E Used to Measure Resistive Elements Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 17 37.3.1 ESIDEBUG1 Register ..................37.3.2 ESIDEBUG2 Register ..................37.3.3 ESIDEBUG3 Register ..................37.3.4 ESIDEBUG4 Register ..................37.3.5 ESIDEBUG5 Register ....................37.3.6 ESICNT0 Register SLAU367P – October 2012 – Revised April 2020 Contents Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 18 38.2.5 EnergyTrace++ Technology 1021 ....................38.2.6 Clock Control 1021 ....................38.2.7 Debug Modes 1021 ..................... 38.3 EEM Configurations 1021 ........................Revision History 1023 Contents SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 19: Table Of Contents
4-8. PUSH SP, POP SP Sequence ........................4-9. SR Bits ................4-10. Register-Byte and Byte-Register Operation ....................4-11. Register-Word Operation SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 20 4-57. Swap Bytes SWPBX[.W] Register Mode ................... 4-58. Swap Bytes SWPBX[.W] In Memory ..................... 4-59. Sign Extend SXTX.A ....................4-60. Sign Extend SXTX[.W] List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 21 ......................11-12. DMAxSA Register ......................11-13. DMAxDA Register ......................11-14. DMAxSZ Register ......................11-15. DMAIV Register ......................12-1. PxIV Register SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 22 ....................16-5. CRC32DIRBW0 Register ....................16-6. CRC32DIRBW1 Register ....................16-7. CRC32INIRESW0 Register ....................16-8. CRC32INIRESW1 Register ....................16-9. CRC32RESRW0 Register List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 23 ................ 21-13. SAPH or SAPH_A Analog Input Signal Chain ......................21-14. Before Excitation ........................21-15. Excitation ......................21-16. Before Reception SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 24 ................21-61. SAPHATM_E/SAPH_AATM_E Register ................21-62. SAPHATM_F/SAPH_AATM_F Register ................21-63. SAPHTBCTL/SAPH_ATBCTL Register ................21-64. SAPHATIMLO/SAPH_AATIMLO Register ................21-65. SAPHATIMHI/SAPH_AATIMHI Register List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 25 22-43. SDHSDT Register ....................22-44. SDHSWINHITH Register ....................22-45. SDHSWINLOTH Register ....................22-46. SDHSDTCDA Register ......................23-1. MTIF Use Case SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 26 26-12. Output Example – Timer in Up Mode ................ 26-13. Output Example – Timer in Continuous Mode ................26-14. Output Example – Timer in Up/Down Mode List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 27 ....................... 29-6. RTCCTL1 Register ....................... 29-7. RTCCTL3 Register ....................... 29-8. RTCOCAL Register ...................... 29-9. RTCTCMP Register ......................29-10. RTCNT1 Register SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 28 30-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) ......................30-2. Character Format ......................30-3. Idle-Line Format ..................30-4. Address-Bit Multiprocessor Format List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 29 ....................32-8. I C Time-Line Legend ..................... 32-9. I C Slave Transmitter Mode ....................32-10. I C Slave Receiver Mode SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 30 ......................34-20. ADC12HI Register ....................... 34-21. ADC12LO Register ..................... 34-22. ADC12IER0 Register ..................... 34-23. ADC12IER1 Register ..................... 34-24. ADC12IER2 Register List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 31 37-7. Analog Hysteresis With DAC Registers ................. 37-8. Timing State Machine Block Diagram ...................... 37-9. Test Cycle Insertion ..................37-10. Timing State Machine Example SLAU367P – October 2012 – Revised April 2020 List of Figures Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 32 1014 ........37-45. Extended Scan Interface Processing State Machine Table Entry Register 1016 ..................38-1. Large Implementation of EEM 1019 List of Figures SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 33 Source and Destination Addressing ................. 4-4. MSP430 Double-Operand Instructions .................. 4-5. MSP430 Single-Operand Instructions ................... 4-6. Conditional Jump Instructions ....................4-7. Emulated Instructions SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 34 ..................9-13. MPUSAM Register Description ..................9-14. MPUIPC0 Register Description ..................9-15. MPUIPSEGB2 Register Description ..................9-16. MPUIPSEGB1 Register Description List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 35 ..................14-13. AESACTL1 Register Description ..................14-14. AESASTAT Register Description ..................14-15. AESAKEY Register Description ..................14-16. AESADIN Register Description SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 36 20-3. HSPLLMIS Register Field Descriptions ................20-4. HSPLLRIS Register Field Descriptions ................20-5. HSPLLIMSC Register Field Descriptions ................20-6. HSPLLICR Register Field Descriptions List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 37 21-41. SAPHAPHIZ/SAPH_AAPHIZ Register Field Descriptions ............21-42. SAPHATM_A/SAPH_AATM_A Register Field Descriptions ............21-43. SAPHATM_B/SAPH_AATM_B Register Field Descriptions ............21-44. SAPHATM_C/SAPH_AATM_C Register Field Descriptions SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 38 23-9. MTIFPGSR Register Field Descriptions ................23-10. MTIFPCCNF Register Field Descriptions ................. 23-11. MTIFPCR Register Field Descriptions ................23-12. MTIFPCCTL Register Field Descriptions List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 39 ..................28-21. RTCAHOUR Register Description ..................28-22. RTCAHOUR Register Description ..................28-23. RTCADOW Register Description ..................28-24. RTCADAY Register Description SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 40 ..................29-38. RTCPS1 Register Description ..................... 29-39. RTCIV Register Description ..................29-40. BIN2BCD Register Description ..................29-41. BCD2BIN Register Description List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 41 ..................31-12. UCBxCTLW0 Register Description ..................31-13. UCBxBRW Register Description ..................31-14. UCBxSTATW Register Description ..................31-15. UCBxRXBUF Register Description SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 42 ................... 35-2. CECTL0 Register Description ................... 35-3. CECTL1 Register Description ................... 35-4. CECTL2 Register Description ................... 35-5. CECTL3 Register Description List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 43 37-26. ESIPSM Register Description 1008 ..................37-27. ESIOSC Register Description 1009 ..................37-28. ESICTL Register Description 1010 ..................37-29. ESITHR1 Register Description 1012 SLAU367P – October 2012 – Revised April 2020 List of Tables Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 44 37-33. ESITSMx Register Description 1014 ........37-34. Extended Scan Interface Processing State Machine Table Entry Description 1016 ..................... 38-1. EEM Configurations 1022 List of Tables SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 45 Memory data bus Most-significant bit Most-significant digit (Non)-Maskable interrupt; also split to UNMI (user NMI) and SNMI (system NMI) Program counter SLAU367P – October 2012 – Revised April 2020 Read This First Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 46 -[0],-[1] Condition after BOR -{0},-{1} Condition after brownout Trademarks MSP430, EnergyTrace are trademarks of Texas Instruments. IAR Embedded Workbench is a trademark of IAR. Read This First SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 47 ..................1.14 Device Descriptor Table ....................1.15 SFR Registers ....................1.16 SYS Registers SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 48 NOTE: The number and type of resets available may vary from device to device. See the device- specific data sheet for all reset sources available. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 49: Bor, Por, And Puc Reset Circuit
MCLK Module PUCs PUC Logic Figure 1-1. BOR, POR, and PUC Reset Circuit SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 50: Interrupt Priority
Module_C_int MAB - 6LSBs Module_D_int low priority Figure 1-2. Interrupt Priority System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 51 Each individual peripheral interrupt is discussed in its respective module chapter in this manual. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 52: Interrupt Processing
The rules above apply to all instructions that set or clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 53: Return From Interrupt
… Watchdog timer WDTIFG Maskable Device specific … … Reserved Maskable … Lowest SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 54 SYSRSTIV, SYSSNIV, SYSUNIV register automatically resets all pending interrupt flags of the group. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 55 ; Return SBD_ISR: ; Vector 22 ; Task_22 starts here RETI ; Return SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 56 See the chapter for further details. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 57: Operation Modes
‡ An enabled reset always restarts the device Arbitrary transitions Figure 1-5. Operation Modes SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 58: Operation Modes
LPM1 LPM2 LPM2 LPM2 LPM0 LPM3 LPM3 LPM3 LPM1 LPM4 LPM4 LPM3 LPM1 System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 59 The abbreviation "LPMx.5" is used in this document to indicate both LPM3.5 and LPM4.5. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 60 A power cycle. Either the SVSHIFG or none of the PMMIFGs is set. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 61 Calculated branching and fast table lookups should be used in place of flag polling and long software calculations. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 62: Connection Of Unused Pins
The SYSJTAGPIN is a write only once function. Clearing it by software is not possible. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 63 Providing entry password for device lock or unlock protection • Run-time data exchange (RTDX) SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 64 Signature 1 (memory location 0FF80h) and JTAG Signature 2 (memory location 0FF82h) control the behavior of the device locking mechanism. NOTE: When a device has been protected, Texas Instruments cannot access the device for a customer return. Access is only possible if a BSL is provided with its corresponding key or an unlock mechanism is provided by the customer.
- Page 65 The complete device descriptor table and its contents can be found in the device-specific data sheet. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 66: Devices Descriptor Table
For example, if Info_length = 5, then the length of the descriptors equals 128 bytes. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 67: Tag Values
// No TLV descriptor found with a matching d_ID_value Return a failing condition SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 68: Ref Calibration Tags
1.14.3.2 ADC Offset and Gain Calibration Table 1-7 shows the ADC calibration tags. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 69: Adc Calibration Tags
Temp, in °C, is the temperature of interest. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 70: Random Number Tags
UART interface selected I2C interface selected 02h to FFh Reserved for future communication interface reserved System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 71: Bsl_Cif_Config Values
Table 1-11 shows the defined configuration options for the given BSL communication interface. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 72: 1.15 Sfr Registers
Reset Pin Control Read/write Word 001Ch Section 1.15.3 SFRRPCR_L Read/write Byte SFRRPCR_H Read/write Byte System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 73: Sfrie1 Register
MOV.B or CLR.B instruction. 0b = Interrupts disabled 1b = Interrupts enabled SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 74: Sfrifg1 Register
WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 75: Sfrrpcr Register
On some devices this bit can be written, but it must always be written as 1. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 76: 1.16 Sys Registers
Word 0000h Section 1.16.8 SYSRSTIV Reset Vector Generator Read Word 0002h Section 1.16.9 System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 77: Sysctl Register
RAM. Care must be taken to avoid address conflicts if LEA is used in this case. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 78: Sysjmbc Register
0b = JMBI0 has no new data. 1b = JMBI0 has new data available. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 79: Sysjmbi0 Register
JTAG mailbox incoming message high byte MSGLO JTAG mailbox incoming message low byte SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 80: Sysjmbo0 Register
JTAG mailbox outgoing message high byte MSGLO JTAG mailbox outgoing message low byte System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 81: Sysuniv Register
NMI flags. See the device-specific data sheet for a list of values. SLAU367P – October 2012 – Revised April 2020 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 82: Sysrstiv Register
See the device-specific data sheet for a list of values. Reset value depends on reset source. System Resets, Interrupts, and Operating Modes, System Control Module SLAU367P – October 2012 – Revised April 2020 (SYS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 83 Topic Page ............ Power Management Module (PMM) Introduction ....................PMM Operation ....................PMM Registers SLAU367P – October 2012 – Revised April 2020 Power Management Module (PMM) and Supply Voltage Supervisor (SVS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 84: Pmm Block Diagram
RTC LDO (32kHz Osc, RTC) CORE Reference SVSH Brownout Figure 2-1. PMM Block Diagram Power Management Module (PMM) and Supply Voltage Supervisor (SVS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 85: Voltage Failure And Resulting Pmm Actions
Voltage H_IT+ H_IT- Time Figure 2-2. Voltage Failure and Resulting PMM Actions SLAU367P – October 2012 – Revised April 2020 Power Management Module (PMM) and Supply Voltage Supervisor (SVS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 86: Pmm Action At Device Power-Up
SVS is enabled and a brownout condition occurs. It sustains this reset until the input power is sufficient for the logic, for proper reset of the system. Power Management Module (PMM) and Supply Voltage Supervisor (SVS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 87 During the undervoltage event, external voltage changes on the pin are not registered internally. This helps prevent erratic behavior from occurring. SLAU367P – October 2012 – Revised April 2020 Power Management Module (PMM) and Supply Voltage Supervisor (SVS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 88: Pmm Registers
Section 2.3.4 PM5CTL0_L Read/write Byte PM5CTL0_H Read/write Byte PMMCTL1 can be written as word only. Power Management Module (PMM) and Supply Voltage Supervisor (SVS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 89: Pmmctl0 Register
1b = Set to 1 to trigger a BOR Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 Power Management Module (PMM) and Supply Voltage Supervisor (SVS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 90: Pmmctl1 Register
Table 2-3. PMMCTL1 Register Description Field Type Reset Description 15-0 Reserved 9600h Reserved. Always reads as 9600h. Power Management Module (PMM) and Supply Voltage Supervisor (SVS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 91: Pmmifg Register
0b = Reset not due to PMMSWBOR 1b = Reset due to PMMSWBOR Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 Power Management Module (PMM) and Supply Voltage Supervisor (SVS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 92: Pm5Ctl0 Register
0b = I/O pin and LPMx.5 configurations unlocked. 1b = I/O pin and LPMx.5 configuration remains locked. Power Management Module (PMM) and Supply Voltage Supervisor (SVS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 93 This chapter describes the operation of the clock system, which is implemented in all devices..........................Topic Page .................. Clock System Introduction ..................Clock System Operation ..................MemoryMap Registers SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 94 NOTE: Not all devices contain both LFXT and HFXT clock sources. See the device-specific data sheet for availability. Figure 3-1 shows the block diagram of the clock system module. Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 95: Clock System Block Diagram
MODOSC Enable Logic LFMODCLK /128 MODOSC MODCLK † Not available on all devices Figure 3-1. Clock System Block Diagram SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 96 LFXT is a source for SMCLK (SELSx = 0) and in active mode (AM) through LPM1 (SMCLKOFF = 0) Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 97: Hffreq Settings
If the application requires or desires to keep HFXT enabled during a low-power mode, the HFXTOFF bit can be cleared before entering the low-power mode. This causes HFXT to remain enabled. SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 98 DCORSEL bits causes the DCOCLK to be held for four clock cycles before releasing the new value into the system. This allows for the DCO to settle properly. Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 99: Module Request Clock System
SMCLKREQEN for the respective clocks. This does not disable fail-safe clock requests; for example, those of the watchdog timer or the clock system itself. SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 100: System Clocks, Power Modes, And Clock Requests
Section 1.4.3 after wakeup from LPM3.5 or LPM4.5, because all CS registers are reset to default values. Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 101: Oscillator Fault Logic
HFXT_OscFault signal is cleared. This counter can be disabled by clearing ENSTFCNT2. The disabling of the counters is valid for bypass and normal modes of operation. SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 102: Switch Mclk From Dcoclk To Lfxtclk
The new clock source is selected and continues with a full high period. Select ACLK DCOCLK ACLK MCLK Wait for DCOCLK ACLK ACLK Figure 3-4. Switch MCLK From DCOCLK to LFXTCLK Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 103: Memorymap Registers
Clock System Control 4 Section 3.3.5 CTL5 Clock System Control 5 Section 3.3.6 CTL6 Clock System Control 6 Section 3.3.7 SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 104: Ctl0 Register
CS registers are available for writing. A5h (W) = 0xA5 RESERVED Reserved. Always reads as 0. Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 105: Ctl1 Register
If DCORSEL = 1: Reserved. Defaults to 24. It is not recommended to use this setting RESERVED Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 106: Ctl2 Register
3h (R/W) = DCOCLK : DCOCLK 4h (R/W) = MODCLK : MODCLK 5h (R/W) = HFXTCLK : HFXTCLK when HFXT available, otherwise DCOCLK Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 107: Ctl3 Register
2h (R/W) = 4 : /4 3h (R/W) = 8 : /8 4h (R/W) = 16 : /16 5h (R/W) = 32 : /32 SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 108: Ctl4 Register
1h (R/W) = VLO is off if it is not used as a source for ACLK, MCLK, or SMCLK or if not used as a source for the RTC in LPM3.5 Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 109 1h (R/W) = LFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 110: Ctl5 Register
0h (R/W) = No fault condition occurred after the last reset 1h (R/W) = LFXT fault; an LFXT fault occurred after the last reset Clock System (CS) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 111: Ctl6 Register
0h (R/W) = DISABLE : ACLK conditional requests are disabled 1h (R/W) = ENABLE : ACLK conditional requests are enabled SLAU367P – October 2012 – Revised April 2020 Clock System (CS) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 112 ..............MSP430X CPU (CPUX) Introduction ......................Interrupts ....................CPU Registers .................... Addressing Modes ..............MSP430 and MSP430X Instructions ................Instruction Set Description CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 113 Direct memory-to-memory transfers without intermediate register holding • Byte, word, and 20-bit address-word addressing Figure 4-1 shows the block diagram of the MSP430X CPU. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 114: Msp430X Cpu Block Diagram
General Purpose General Purpose General Purpose General Purpose Zero, Z Carry, C MCLK 16/20-bit ALU Overflow,V Negative,N Figure 4-1. MSP430X CPU Block Diagram CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 115: Pc Storage On The Stack For Interrupts
20-bit PC is restored making return from interrupt to any address in the memory range possible. Item n−1 PC.15:0 PC.19:16 SR.11:0 Figure 4-2. PC Storage on the Stack for Interrupts SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 116: Program Counter
Figure 4-5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 117: Stack Pointer
Figure 4-9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable operation can result. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 118: Sr Bits
Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and BIC. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 119: Values Of Constant Generators Cg1, Cg2
#0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD #1,dst SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 120: Register-Byte And Byte-Register Operation
Register-Word Operation High Byte Low Byte 19 16 15 Register used Memory Operation Memory Figure 4-11. Register-Word Operation CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 121: Word-Register Operation
High Byte Low Byte 19 16 15 Register Unused Memory +2 Memory Operation Memory +2 Memory Figure 4-13. Register – Address-Word Operation SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 122: Address-Word - Register Operation
Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels and have no special meaning. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 123 Register Space Space 21036h xxxxh AA550h 21036h xxxxh AA550h 11111h BB551h 21034h D546h 21034h D546h 21032h 1800h 21032h 1800h AA550h.or.11111h = BB551h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 124: Indexed Mode In Lower 64Kb
The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 125: Indexed Mode In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 4-16. Indexed Mode in Upper Memory SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 126: Overflow And Underflow For Indexed Mode
23456h + F8346h = 1B79Ch. Destination: The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 127: Example For Indexed Mode
07777h 2345h 7777h 17778h 17778h 23456h 1B79Eh xxxxh +F8346h 1B79Eh xxxxh 1B79Ch 5432h 5432h 1B79Ch 1B79Ch Figure 4-18. Example for Indexed Mode SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 128 0001h +32100h 7777Ah 0007h +12345h 77778h 77777h 2345h 7777h 77778h 77778h 23456h +12346h 3579Eh 0006h 3579Eh 0006h 3579Ch 5432h 5432h 3579Ch 3579Ch CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 129 2 words pointed to by R5 + 8002h and R5 + 8002h + 2h which results in address 00100h + F8002h (+2h) = F8102h and F8104h. Destination: Register R6 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 130: Symbolic Mode Running In Lower 64Kb
Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the index for this example. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 131: Symbolic Mode Running In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 4-20. Symbolic Mode Running in Upper Memory SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 132: Overflow And Underflow For Symbolic Mode
3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this example. Destination: Word TONI located at address 00778h pointed to by the absolute address 00778h CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 133 2F036h 3379Eh xxxxh +04766h 3379Eh xxxxh 3379Ch 5432h 5432h 3379Ch 3379Ch 5432h 0077Ah xxxxh 0077Ah xxxxh +2345h 7777h 2345h 7777h 00778h 00778h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 134 7777Ah xxxxh +56740h 7777Ah xxxxh +45h 77778h xx45h xx77h 77778h 77778h 21036h +14766h 3579Eh xxxxh 3579Eh xxxxh 3579Ch xx32h xx32h 3579Ch 3579Ch CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 135 5292h 21034h 21034h 5432h 0777Ah xxxxh 0777Ah xxxxh +2345h 7777h 2345h 7777h 07778h 07778h 0579Eh xxxxh 0579Eh xxxxh 5432h 5432h 0579Ch 0579Ch SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 136 1987h 21032h 21032h 65432h 7777Ah 0001h 7777Ah 0007h +12345h 77777h 2345h 7777h 77778h 77778h 3579Eh 0006h 3579Eh 0006h 5432h 5432h 3579Ch 3579Ch CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 137 45678h 5432h 4777Ah xxxxh +02100h 4777Ah xxxxh +2345h 47778h 7777h 2345h 7777h 47778h 47778h 3579Eh xxxxh 3579Eh xxxxh 5432h 5432h 3579Ch 3579Ch SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 138 00778h 55F6h 55F6h 21034h 21034h 00778h 0077Ah xxxxh +0000h 0077Ah xxxxh +45h 00778h xx45h xx77h 00778h 00778h 3579Dh 3579Dh xx32h 3579Ch 3579Ch CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 139 0778h 21038h 0778h 3456h 3456h 21036h 21036h 50B2h 50B2h 21034h 21034h 3456h 0077Ah xxxxh 0077Ah xxxxh +2345h 579Bh 2345h 579Bh 00778h 00778h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 140 3456h 21036h 3456h 50F2h 50F2h 21034h 21034h 1907h 1907h 21032h 21032h 23456h 7777Ah 0001h 7777Ah 0003h +12345h 3579Bh 2345h 579Bh 77778h 77778h CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 141: Msp430 Double-Operand Instruction Format
Table 4-4 lists the 12 MSP430 double-operand instructions. Op-code Rsrc Rdst Source or Destination 15:0 Destination 15:0 Figure 4-22. MSP430 Double-Operand Instruction Format SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 142: Msp430 Single-Operand Instructions
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 143: Format Of Conditional Jump Instructions
* = Status bit is affected – = Status bit is not affected 0 = Status bit is cleared 1 = Status bit is set SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 144: Interrupt, Return, And Reset Cycles And Length
Instruction PUSH CALL SWPB, SXT SWPB R5 RRC @R9 @Rn+ SWPB @R10+ CALL #LABEL X(Rn) CALL 2(R7) PUSH EDE &EDE SXT &EDE CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 145: Msp430 Format I Instructions Cycles And Length
BR &EDE &EDE TONI MOV &EDE,TONI x(Rm) MOV &EDE,0(SP) MOV &EDE,&TONI &TONI MOV, BIT, and CMP instructions execute in 1 fewer cycle. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 146: Extension Word For Register Modes
Table 4-12. An example is shown in Figure 4-28. Source bits 19:16 Destination bits 19:16 Figure 4-26. Extension Word for Non-Register Modes CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 147: Example For Extended Register Or Register Instruction
8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 4-27. Example for Extended Register or Register Instruction SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 148: Example For Extended Immediate Or Indexed Instruction
* = Status bit is affected – = Status bit is not affected 0 = Status bit is cleared 1 = Status bit is set CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 149: Extended Format I Instruction Formats
(see Figure 4-30). Address+2 ..................19:16 Operand LSBs 15:0 Address Figure 4-30. 20-Bit Addresses in Memory SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 150: Extended Format Ii Instruction Format
Format II instructions. n−1/Rn Op-code Op-code dst.19:16 Op-code dst.15:0 Figure 4-31. Extended Format II Instruction Format CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 151: Pushm And Popm Instruction Format
Figure 4-34. BRA Instruction Format Op-code Rdst Op-code Rdst index15:0 Op-code #imm/ix/abs19:16 #imm15:0 / index15:0 / &abs15:0 Figure 4-35. CALLA Instruction Format SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 152: Extended Emulated Instructions
Test Rdst (compare with 0) TSTX(.B,.A) dst CMPX(.B,.A) #0,dst Test dst (compare with 0) POPX dst MOVX(.B, .A) @SP+,dst Pop to dst CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 153: Address Instructions, Operate On 20-Bit Register Data
* = Status bit is affected – = Status bit is not affected 0 = Status bit is cleared 1 = Status bit is set SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 154: Msp430X Format Ii Instruction Cycles And Length
5, 3 5, 3 POPX.A 4, 2 – – – 7, 3 7, 3 7, 3 Add 1 cycle when Rn = SP CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 155: Msp430X Format I Instruction Cycles And Length
Reduce the cycle count by 2 for MOV, BIT, and CMP instructions. Reduce the cycle count by 1 for MOV, ADD, and SUB instructions. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 156: Address Instruction Cycles And Length
– – MOVA 2(R6),PC – – MOVA EDE,R8 – – MOVA EDE,PC – – MOVA &EDE,R8 &EDE MOVA &EDE,PC – – CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 157: Instruction Map Of Msp430X
SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx BIC, BIC.B Dxxx BIS, BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 158 RRCM.W n – 1 RRAM.W n – 1 RRAM.W #n,Rdst RLAM.W #n,Rdst RLAM.W n – 1 RRUM.W n – 1 RRUM.W #n,Rdst CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 159 POPM.A #n,Rdst POPM.A n – 1 dst – n + 1 POPM.W #n,Rdst POPM.W n – 1 dst – n + 1 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 160 Instruction Set Description www.ti.com 4.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 161 The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 162 The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B @R5+,R6 ; Add byte to R6. R5 + 1. R6: 000xxh TONI ; Jump if no carry ; Carry occurred CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 163 ADDC.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 164 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 165 A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 166 A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 167 ; Test I/O port P1 bits. R5 + 1 TONI ; No corresponding bit is set ; At least 1 bit is set SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 168 ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 169 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL ; Start address at @R5 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 170 TONI ; 0 -> TONI Example Register R5 is cleared. Example RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 171 @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter DADC 2(R12) ; add carry to high word of 32-bit counter SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 172 CLRN CALL SUBR .... SUBR SUBRET ; If input is negative: do nothing and return ....SUBRET CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 173 (R5 + X); for example, a table with addresses starting at X. The address is within the lower 64KB. X is within ±32KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 174 Jump to label TONI if values are equal. The next table byte is addressed. CMP.B @R5+,&P1OUT ; Compare P1 bits with table. R5 + 1 TONI ; Equal contents ; Not equal CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 175 ; Reset carry ; next instruction's start condition is defined DADD.B R5,0(R8) ; Add LSDs + C DADC 1(R8) ; Add carry to MSDs SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 176 2-digit BCD number contained in R4. The carry C is added, also. R4.19:8 = 0 CLRC ; Clear carry DADD.B &BCD,R4 ; Add BCD to R4 decimally. R4: 0,00ddh CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 177: Decrement Overlap
Do not transfer tables using the routine above with the overlap shown in Figure 4-36. TONI EDE+254 TONI+254 Figure 4-36. Decrement Overlap SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 178 DECD Example Memory at location LEO is decremented by 2. DECD.B ; Decrement MEM(LEO) Decrement status byte STATUS by 2 DECD.B STATUS CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 179 The rules above apply to all instructions that clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 180 The rules above apply to all instructions that set the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 181 The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B STATUS CMP.B #11,STATUS OVFL SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 182 The byte on the top of the stack is incremented by 2. INCD.B 0(SP) ; Byte on TOS is increment by 2 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 183 Content of memory byte LEO is negated. MOV.B #0AEh,LEO MEM(LEO) = 0AEh INV.B ; Invert LEO, MEM(LEO) = 051h INC.B ; MEM(LEO) is negated, MEM(LEO) = 052h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 184 ; Is R5 >= 12345h? Info to C Label2 ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 185 R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA #1,R7 ; Increment R7 Label4 ; Zero reached: Go to Label4 ; R7 not equal 0. Continue here. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 186 CMPA #12345h,R5 ; Is R5 >= 12345h? Label2 ; Yes, 12344h < R5 <= 7FFFFh ; No, 80000h <= R5 < 12345h CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 187 CMPA #12345h,R5 ; Is R5 < 12345h? Label2 ; Yes, 80000h =< R5 < 12345h ; No, 12344h < R5 <= 7FFFFh SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 188 ; No Timer_A interrupt pending IHCCR1 ; Timer block 1 caused interrupt IHCCR2 ; Timer block 2 caused interrupt RETI ; No legal interrupt, return CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 189 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; R7 < 0: Go to Label4 ; R7 >= 0. Continue here. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 190 TONI is within PC ± 32 K. TONI,R5 ; TONI + R5 -> R5. Carry -> C Label0 ; No carry ; Carry = 1: continue here CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 191 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 192 Loop MOV.B @R10+,TOM-EDE-1(R10) ; R10 points to both tables. ; R10+1 ; Decrement counter Loop ; Not yet done ; Copy completed CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 193 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 194 ; Last word on stack moved to the SR NOTE: System stack pointer The system SP is always incremented by 2, independent of the byte suffix. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 195 Save the 2 bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B ; Save EDE xxXXh PUSH.B TONI ; Save TONI xxYYh SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 196: Stack After A Ret Instruction
; Return to lower 64 K Item n Item n Return Stack before RET Stack after RET instruction instruction Figure 4-37. Stack After a RET Instruction CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 197 ; Interrupt handler code POPM.A #2,R14 ; Restore R13 and R14 (20-bit data) RETI ; Return to 20-bit address in full memory range SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 198: Destination Operand-Arithmetic Shift Left
The assembler does not recognize the instructions: @R5+ RLA.B @R5+ RLA(.B) @R5 They must be substituted by: @R5+,-2(R5) ADD.B @R5+,-1(R5) ADD(.B) @R5 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 199: Destination Operand-Carry Left Shift
The assembler does not recognize the instructions: @R5+ RLC.B @R5+ RLC(.B) @R5 They must be substituted by: ADDC @R5+,-2(R5) ADDC.B @R5+,-1(R5) ADDC(.B) @R5 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 200: Rotate Right Arithmetically Rra.b And Rra.w
The signed RAM byte EDE is shifted arithmetically right 1 position. RRA.B ; EDE/2 -> EDE Figure 4-40. Rotate Right Arithmetically RRA.B and RRA.W CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 201: Rotate Right Through Carry Rrc.b And Rrc.w
; Prepare carry for MSB ; EDE = EDE >> 1 + 8000h Figure 4-41. Rotate Right Through Carry RRC.B and RRC.W SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 202 ; Subtract LSDs SBC.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 203 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 204 The negative bit (N) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 205 The zero bit (Z) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 206 Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 207 Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64 K. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 208: Swap Bytes In Memory
Figure 4-42. Swap Bytes in Memory Before SWPB High Byte Low Byte After SWPB Low Byte High Byte Figure 4-43. Swap Bytes in a Register CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 209 R7. MOV.B EDE,R5 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ADDA R5,R7 ; Add signed 20-bit values SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 210 ; Low byte of R7 is positive but not zero R7NEG ..; Low byte of R7 is negative R7ZERO ..; Low byte of R7 is zero CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 211 R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B EDE,R7 ; Set different bits to 1 in R7. INV.B ; Invert low byte of R7, high byte is 0h SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 212 20-bit values when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 213 The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A @R12 ; Increment lower 20 bits ADCX.A @R13 ; Add carry to upper 20 bits SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 214 ; Jump if no carry ; Carry occurred Note: Use ADDA for the following 2 cases for better code density and execution. ADDX.A Rsrc,Rdst ADDX.A #imm20,Rdst CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 215 ADDCX.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 216 A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 217 A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 218 A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 219 ; Test input P1 bits. R5 + 1 TONI ; No corresponding input bit is set ; At least 1 bit is set SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 220 Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is cleared. CLRX.A TONI ; 0 -> TONI CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 221 ; Equal contents ; Not equal Note: Use CMPA for the following cases for better density and execution. CMPA Rsrc,Rdst CMPA #imm20,Rdst SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 222 The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) ; Increment lower 20 bits DADCX.A 0(R13) ; Add carry to upper 20 bits CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 223 The 2-digit BCD number contained in 20-bit address BCD is added decimally to a 2-digit BCD number contained in R4. CLRC ; Clear carry DADDX.B BCD,R4 ; Add BCD to R4 decimally. ; R4: 000ddh SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 224 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by 1. DECX.A TONI ; Decrement TONI CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 225 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by 2. DECDX.A TONI ; Decrement TONI SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 226 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-wordTONI is incremented by 1. INCX.A TONI ; Increment TONI (20-bits) CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 227 OSCOFF, CPUOFF, and GIE are not affected. Example RAM byte LEO is incremented by 2; PC points to upper memory. INCDX.B ; Increment LEO by 2 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 228 Content of memory byte LEO is negated. PC is pointing to upper memory. INVX.B ; Invert LEO INCX.B ; MEM(LEO) is negated CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 229 ; Indirect,Auto/Reg MOVX.A Rsrc,&abs20 MOVA Rsrc,&abs20 ; Reg/Absolute The next 4 replacements are possible only if 16-bit indexes are sufficient for the addressing: SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 230 MOVA z16(Rsrc),Rdst ; Indexed/Reg MOVX.A Rsrc,z20(Rdst) MOVA Rsrc,z16(Rdst) ; Reg/Indexed MOVX.A symb20,Rdst MOVA symb16,Rdst ; Symbolic/Reg MOVX.A Rsrc,symb20 MOVA Rsrc,symb16 ; Reg/Symbolic CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 231 Example Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 232 Save the 5 16-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 233 &EDE ; Write word to address EDE Example Write the 20-bit value on TOS to R9 POPX.A ; Write address-word to R9 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 234 ; Save byte at address EDE Example Save the 20-bit value in R9 on the stack. PUSHX.A ; Save address-word in R9 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 235: Rotate Left Arithmetically-Rlam[.W] And Rlam.a
The 20-bit operand in R5 is shifted left by 3 positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 0000 Figure 4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 236: Destination Operand-Arithmetic Shift Left
Example The 20-bit value in R7 is multiplied by 2 RLAX.A ; Shift left R7 (20-bit) Figure 4-45. Destination Operand-Arithmetic Shift Left CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 237: Destination Operand-Carry Left Shift
The RAM byte LEO is shifted left 1 position. PC is pointing to upper memory. RLCX.B ; RAM(LEO) x 2 + C -> RAM(LEO) Figure 4-46. Destination Operand-Carry Left Shift SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 238: Rotate Right Arithmetically Rram[.W] And Rram.a
#1,R15 ; (1.5 y R15) y 0.5 = 0.75 y R15 -> R15 0000 Figure 4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 239 The signed 20-bit number in R5 is shifted arithmetically right 4 positions. RRAX.A ; R5/16 -> R5 Example The signed 8-bit value in EDE is multiplied by 0.5. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 240: Rotate Right Arithmetically Rrax(.B,.A) - Register Mode
; EDE/2 -> EDE 0000 Figure 4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode Figure 4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 241 Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) Reset Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 242: Rotate Right Through Carry Rrcm[.W] And Rrcm.a
MSB–1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 Figure 4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 243 ; Prepare carry for MSB RRCX.A ; EDE = EDE » 1 + 80000h Example The word in R6 is shifted right by 12 positions. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 244: Rotate Right Through Carry Rrcx(.B,.A) - Register Mode
0 − − − − − − − − − − − − − − − − − − − − 0 Figure 4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode Figure 4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 245: Rotate Right Unsigned Rrum[.W] And Rrum.a
The word in R6 is shifted right by 1 bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 0000 Figure 4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 246: Rotate Right Unsigned Rrux(.B,.A) - Register Mode
0 − − − − − − − − − − − − − − − − − − − − 0 Figure 4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 247 ; Subtract LSDs SBCX.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 248 ; Subtract CNT from @R12 Note: Use SUBA for the following 2 cases for better density and execution. SUBX.A Rsrc,Rdst SUBX.A #imm20,Rdst CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 249 Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 250: Swap Bytes Swpbx.a Register Mode
Figure 4-55. Swap Bytes SWPBX.A Register Mode Before SWPBX.A High Byte Low Byte After SWPBX.A Low Byte High Byte Figure 4-56. Swap Bytes SWPBX.A In Memory CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 251: Swap Bytes Swpbx[.W] Register Mode
Figure 4-57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX High Byte Low Byte After SWPBX Low Byte High Byte Figure 4-58. Swap Bytes SWPBX[.W] In Memory SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 252: Sign Extend Sxtx.a
8 7 6 SXTX.A dst 8 7 6 ..Figure 4-59. Sign Extend SXTX.A SXTX[.W] Rdst SXTX[.W] dst Figure 4-60. Sign Extend SXTX[.W] CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 253 ; LEO is zero LEOPOS ..; LEO is positive but not zero LEONEG ..; LEO is negative LEOZERO ..; LEO is zero SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 254 (20-bit address) XORX.B EDE,R7 ; Set different bits to 1 in R7 INV.B ; Invert low byte of R7. R7.19:8 = 0. CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 255 MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. The MSP430X address instructions are listed and described in the following pages. SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 256 R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA #0A4320h,R5 ; Add A4320h to 20-bit R5 TONI ; Jump on carry ; No carry occurred CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 257 Indirect mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. ; MOVA @R5,PC SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 258 Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 259 Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA ; Start address at @R5 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 260 LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 ± 32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 261 The destination register is cleared. Status Bits Status bits are not affected. Example The 20-bit value in R10 is cleared. CLRA ; 0 -> R10 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 262 R6, the program continues at label GRE. CMPA R6,R5 ; Compare R6 with R5 (R5 - R6) ; R5 >= R6 ; R5 < R6 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 263 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is decremented by 2. DECDA ; Decrement R5 by 2 SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 264 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is incremented by 2. INCDA ; Increment R5 by 2 CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 265 Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 266 Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ± 32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 267 ; Save R14 and R13 (20 bit data) ; Subroutine code POPM.A #2,R14 ; Restore R13 and R14 (20 bit data) RETA ; Return (to full address space) SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 268 The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA R5,R6 ; R6 - R5 -> R6 TONI ; Carry occurred ; No carry CPUX SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 269 ; R7 is zero R7POS ..; R7 is positive but not zero R7NEG ..; R7 is negative R7ZERO ..; R7 is zero SLAU367P – October 2012 – Revised April 2020 CPUX Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 270 This chapter describes the 32-bit hardware multiplier (MPY32). The MPY32 module is implemented in all devices..........................Topic Page ..........32-Bit Hardware Multiplier (MPY32) Introduction ....................MPY32 Operation ....................MPY32 Registers 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 271 8-bit and 24-bit multiplications without requiring a "sign extend" instruction The MPY32 block diagram is shown in Figure 5-1. SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 272: Mpy32 Block Diagram
MPYSAT 32-bit Adder MPYFRAC MPYC 32-bit Demultiplexer SUMEXT RES3 RES2 RES1/RESHI RES0/RESLO 32-bit Multiplexer Figure 5-1. MPY32 Block Diagram 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 273: Result Availability (Mpyfrac = 0, Mpysat = 0)
24/32 × 8/16 OP2 written OP2L written 8/16 × 24/32 OP2H written OP2L written 24/32 × 24/32 OP2H written SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 274: Op1 Registers
During the execution of the 16-bit operation, the content of the high-word is ignored. 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 275: Mode
00000h = Result was positive or zero 0 = No carry for result 0FFFFh = Result was negative 1 = Result has a carry SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 276 ; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&MPYS_B ; Load 1st operand MOV.B #034h,&OP2_B ; Load 2nd operand ; Process results 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 277: Q15 Format Representation
In fractional mode, the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for 16×16-bit operations and bits 64 and 65 for 32×32-bit operations – not only bits 32 or 64, respectively. SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 278: Result Availability In Fractional Mode (Mpyfrac = 1, Mpysat = 0)
&K2,&OP2 ; Load K2 to get A2*K2 &RES1,&PROD ; Save A1*K1+A2*K2 as result #MPYSAT+MPYFRAC,&MPY32CTL0 ; turn back to normal 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 279: Saturation Flow Chart
14=0 RES0 = 00000h RES0 = 00000h 32-bit Saturation 64-bit Saturation completed completed Figure 5-4. Saturation Flow Chart SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 280 5.2.5 Putting It All Together Figure 5-5 shows the complete multiplication flow, depending on the various selectable modes for the MPY32 module. 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 281: Multiplication Flow Chart
MPYC and bit 15 of unshifted RES1. unshifted RES3. MPYSAT=1 MPYSAT=1 32-bit Saturation 64-bit Saturation Multiplication completed Figure 5-5. Multiplication Flow Chart SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 282 08000 0000h. Adding a negative number to it would again cause an underflow, thus, the final result is also saturated to 08000 0000h. 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 283 ; Interrupts may be enabled before ; processing results if result ; registers are stored and restored in ; interrupt service routines SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 284 DMA. The signal into the DMA controller is 'Multiplier ready' (see the DMA Controller chapter for details). 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 285: Mpy32 Registers
24-bit operand 1 – signed multiply – high byte Read/write Byte Undefined MAC32L 32-bit operand 1 – multiply accumulate – low word Read/write Word Undefined SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 286: Alternative Registers
8-bit operand one – signed multiply accumulate MACS_B or MACS_L MACS32L_B or MACS32L_L 16x16-bit result low word RESLO RES0 16x16-bit result high word RESHI RES1 32-Bit Hardware Multiplier (MPY32) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 287: Mpy32Ctl0 Register
It is used to restore the SUMEXT content in MAC mode. 0b = No carry for result 1b = Result has a carry SLAU367P – October 2012 – Revised April 2020 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 288: Fram Controller Overview
FRPWR bit FRPWR bit FRAM power status Power control when the device FRLPMPWR bit FRPWR bit wakes up from a FRAM Controller Overview SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 289 Wait State Control ....................... FRAM ECC ..................... FRAM Write Back ..................FRAM Power Control ....................FRAM Cache ....................7.10 FRCTL Registers SLAU367P – October 2012 – Revised April 2020 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 290: Fram Controller Block Diagram
UBDRSTEN bit. If an uncorrectable error is detected, a PUC is initiated and the program vectors to the SYSRSTIV. FRAM Controller (FRCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 291: Programming Fram Devices
The device starts with zero wait states. • Correct wait state settings must be ensured, otherwise a PUC might be generated to avoid erratic FRAM accesses. SLAU367P – October 2012 – Revised April 2020 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 292: Fram Ecc
RAM to clear the FRPWR bit for turning off power to FRAM. Figure 7-2 shows the activation flow of the FRAM controller. FRAM Controller (FRCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 293: Fram Power Control Diagram
4 cache lines of 64 bit size. Memory read accesses on consecutive addresses can be executed without wait states when they are within the same cache line. SLAU367P – October 2012 – Revised April 2020 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 294: 7.10 Frctl Registers
Read/Write Byte GCCTL0_H Read/Write Byte GCCTL1 General Control 1 Read/write Word 0000h Section 7.10.3 GCCTL1_L Read/Write Byte GCCTL1_H Read/Write Byte FRAM Controller (FRCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 295: Frctl0 Register
(cache miss). 0 implies no wait states. Reserved Reserved. Must be written as 0. Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 296: Gcctl0 Register
0b = FRAM startup is delayed to the first FRAM access after LPM exit 1b = FRAM is powered up instantly with LPM exit. Reserved Reserved. Always reads as 0. FRAM Controller (FRCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 297: Gcctl1 Register
0b = No interrupt pending 1b = Interrupt pending. Can be cleared by user or by reading SYSSNIV Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 FRAM Controller (FRCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 298 ............FRAM Controller A (FRCTL_A) Operation ....................... FRAM ECC ..................FRAM Power Control ....................FRAM Cache ..................FRCTL_A Registers FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 299: Frctl_A Block Diagram
The UBDRSTEN bit and the UBDIE bit are mutually exclusive. The UBDRSTEN bit has a higher priority—if both bits are set, the UBDIE bit is ignored and the UBDRSTEN bit remains active. SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 300 Thus, the application must write a proper wait state to NWAITS[3:0] before accessing FRAM. See Table 8-1 for optimized wait states with different system frequencies. FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 301: Fram Memory Access Speed
The running speed of the CPU and DMA never exceeds the maximum FRAM access speed limit in debug mode. SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 302: Fram Power Mode Transition
INACTIVE LPM2, LPM3, or LPM4 ACTIVE (FRPWR bit is LPM0 Don't care No → Yes Don't care set automatically) FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 303: Fram Power Control Diagram
FRAM access occurs. In this case, no wait state is required and the data is accessed at the full system bus speed. SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 304 9600h Section 8.6.1 GCCTL0 General Control Register 0 Read-Write Section 8.6.2 GCCTL1 General Control Register 1 Read-Write Section 8.6.3 FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 305: Frctl0 Register
Dh (R/W) = FRAM wait states: 13 Eh (R/W) = FRAM wait states: 14 Fh (R/W) = FRAM wait states: 15 SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 306: Frctl_A Registers
If a write access is attempted, the WPIFG (Write Protection Flag) bit will be set. FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 307: Gcctl0 Register
(WPIFG). 1h (R/W) = WPIE_1 : Enable NMI for the Write Protection Detection flag (WPIFG). Generates vector in SYSSNIV. SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 308 0h (R/W) = FRPWR_0 : Enable INACTIVE mode. 1h (R/W) = FRPWR_1 : Enable ACTIVE mode. Reserved Reserved. Always read 0. Reset type: PUC FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 309: Gcctl1 Register
1h (R/W) = UBDIFG_1 : Interrupt pending. Can be cleared by writing 0 or by reading SYSSNIV when it is the highest pending interrupt. SLAU367P – October 2012 – Revised April 2020 FRAM Controller A (FRCTL_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 310 0 or by reading SYSSNIV if it is the highest pending interrupt. Reserved Reserved. Always read 0. Reset type: PUC FRAM Controller A (FRCTL_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 311 MPU Access Management Settings ....................MPU Violations ......................MPU Lock ............... How to Enable MPU and IPE Segments ....................MPU Registers SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 312: Memory Protection Unit Overview
Memory Protection Unit. Control Registers Main Memory Array/ Violation Controller Figure 9-1. Memory Protection Unit Overview Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 313: Segment Border Register
[14] [13] [12] [11] [10] Figure 9-4. Example of Segment Border Register Fixed Bits When FRAM Size = 256KB SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 314: Segmentation Of Main Memory
Interrupt service routines can be executed from the IPE-segment, too. Table 9-2 summarizes the possible combinations of code execution and memory access types and the resulting access rights. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 315: Ip Encapsulation Access Rights Equivalent Schematic
For the following examples, the segment with the higher address range formed by this border is called the higher segment. The segment with the lower address range is called the lower segment. SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 316: Mpu Border Selection Example 64Kb (004000H To 013Fffh)
The setting of the boundaries for the IP Encapsulation segment follows the same principle as the Main Segment settings. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 317: Segment Access Rights
This causes an access right violation if instruction fetches are not allowed within the neighboring segment. SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 318: Access Rights To Ivt
Guide, the compiler and linker handle the structure generation and initialization automatically - Section 9.6.1 describes what happens behind the scenes in this case, and further user setup is not required. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 319: Ipe Signatures
#define IPE_MPUIPPUC 0x0020 #define IPE_SEGREG(a) (a >> 4) #define IPE_BIP(a,b,c) (a ^ b ^ c ^ 0xFFFF) #define IPE_FILLSTRUCT(a,b,c) SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 320: Ipe_Init_Structure
This mechanism ensures that no exposure of IP code can happen by a misconfiguration or a memory corruption. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 321: Mpu Registers
Memory Protection Unit IP Encapsulation MPUIPSEGB1 Read/Write Word 0000h Segment Border 1 Register MPUIPSEGB1_L Read/Write Byte MPUIPSEGB1_H Read/Write Byte SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 322: Mpuctl0 Register
MPULOCK is not set 0b = Disabled 1b = Enabled Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 323: Mpuctl1 Register
This bit is write 0 only and write 1 has no effect. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 324: Mpusegb2 Register
0 (if MPU is enabled and MPUSEGB1 is also 0, only Segment 3 is active). MPUSEGB2[5:0] = MPU Segment Border 2 address line 9-4 equivalents. Must be written as zero. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 325: Mpusegb1 Register
0 (if MPU is enabled and MPUSEGB2 is also 0, only Segment 3 is active). MPUSEGB1[5:0] = MPU Segment Border 1 address line 9-4 equivalents. Must be written as zero. SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 326: Mpusam Register
0b = Read on Main Memory Segment 3 causes a violation if MPUSEG3WE = MPUSEG3XE = 0 1b = Read on Main Memory Segment 3 is allowed Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 327: Mpusam Register Description
0b = Read on Main Memory Segment 1 causes a violation if MPUSEG1WE = MPUSEG1XE = 0 1b = Read on Main Memory Segment 1 is allowed SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 328: Mpuipc0 Register
1b = Violation in Main Memory Segment 1 asserts the MPUSEGIPIFG bit and executes a PUC Reserved Reserved. Always read 0. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 329: Mpuipsegb2 Register
Segment 3 is active). MPUIPSEGB2[5:0] = MPU IP Segment Border 2 address line 9-4 equivalents. Must be written as zero. SLAU367P – October 2012 – Revised April 2020 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 330: Mpuipsegb1 Register
Segment 3 is active). MPUIPSEGB1[5:0] = MPU Segment Border 1 address line 9-4 equivalents. Must be written as zero. Memory Protection Unit (MPU) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 331 The RAM controller (RAMCTL) allows control of the power-down behavior of the RAM..........................Topic Page ............... 10.1 RAM Controller (RAMCTL) Introduction ................... 10.2 RAMCTL Operation ................... 10.3 RAMCTL Registers SLAU367P – October 2012 – Revised April 2020 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 332: Ram Power Mode Transitions Into And Out Of Lpm3 Or Lpm4
LEA RAM while the DTC is active. If CPU or DMA accesses the LEA RAM while the DTC is accessing the same memory: • A write access from CPU or DMA is ignored RAM Controller (RAMCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 333 DACCESSIE bit. If DACCESSIE = 1 and DACCESSIFG = 1, then a user NMI is generated (DACCESSIFG). See the device-specific data sheet for the user NMI information. SLAU367P – October 2012 – Revised April 2020 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 334: 10.3 Ramctl Registers
Type Reset Section CTL0 RAM Controller Control 0 read-write 6900h Section 10.3.1 CTL1 RAM Controller Control 1 read-write Section 10.3.2 RAM Controller (RAMCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 335: Ctl0 Register
RAM sector. SLAU367P – October 2012 – Revised April 2020 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 336 RAM sector. RAM Controller (RAMCTL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 337: Ctl1 Register
See the device speicfic datasheet for details. 0h (R/W) = DACCESS Interrupt is not pending 1h (R/W) = DACCESS Interrupt is pending. SLAU367P – October 2012 – Revised April 2020 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 338 CPU intervention. This chapter describes the operation of the DMA controller..........................Topic Page ............11.1 Direct Memory Access (DMA) Introduction ....................11.2 DMA Operation ....................11.3 DMA Registers DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 339 • Four addressing modes • Single, block, or burst-block transfer modes The DMA controller block diagram is shown in Figure 11-1. SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 340: Dma Controller Block Diagram
DMAnSA DMAnTRIG0 00000 DMAnTRIG1 00001 DMAnDA DMAnSZ DMASRSBYTE DMAEN DMASRCINCR DMARMWDIS DMAnTRIG31 11111 Halt CPU Figure 11-1. DMA Controller Block Diagram DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 341: Dma Addressing Modes
Address Space Controller Controller Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses Figure 11-2. DMA Addressing Modes SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 342: Dma Transfer Modes
A complete block is transferred with one trigger. DMAEN remains enabled. 110, 111 Repeated burst-block transfer CPU activity is interleaved with a block transfer. DMAEN remains enabled. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 343: Dma Single Transfer State Diagram
AND Trigger = 0] AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 11-3. DMA Single Transfer State Diagram SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 344 In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer starts another block transfer. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 345: Dma Block Transfer State Diagram
DMAxSZ > 0 [DMALEVEL = 1 AND Trigger = 0] Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 11-4. DMA Block Transfer State Diagram SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 346 DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated burst- block mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 347: Dma Burst-Block Transfer State Diagram
AND DMAxSZ = 0] 2 × MCLK Burst State (release CPU for 2 × MCLK) Figure 11-5. DMA Burst-Block Transfer State Diagram SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 348 When DMALEVEL = 1, transfer modes selected when DMADT = {0, 1, 2, 3} are recommended, because the DMAEN bit is automatically reset after the configured transfer. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 349: Dma Trigger Operation
DMA0-DMA1-DMA2, for example, for three channels. When the ROUNDROBIN bit is cleared, the channel priority returns to the default priority. SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 350: Maximum Single-Transfer Dma Cycle Time
(PC) to automatically enter the appropriate software routine. Disabled DMA interrupts do not affect the DMAIV value. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 351 ; Back to main program DMA0_HND ; Vector 2: DMA channel 0 ; Task starts here RETI ; Back to main program SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 352 ADC12IFG flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. Any ADC12IFG flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 353: 11.3 Dma Registers
DMA Channel 6 Source Address Read/write Word, undefined Section 11.3.7 double word DMA6DA DMA Channel 6 Destination Address Read/write Word, undefined Section 11.3.8 double word SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 354 DMA Channel 7 Destination Address Read/write Word, undefined Section 11.3.8 double word DMA7SZ DMA Channel 7 Transfer Size Read/write Word undefined Section 11.3.9 DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 355: Dmactl0 Register
00000b = DMA0TRIG0 00001b = DMA0TRIG1 00010b = DMA0TRIG2 ⋮ 11110b = DMA0TRIG30 11111b = DMA0TRIG31 SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 356: Dmactl1 Register
00000b = DMA2TRIG0 00001b = DMA2TRIG1 00010b = DMA2TRIG2 ⋮ 11110b = DMA2TRIG30 11111b = DMA2TRIG31 DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 357: Dmactl2 Register
00000b = DMA4TRIG0 00001b = DMA4TRIG1 00010b = DMA4TRIG2 ⋮ 11110b = DMA4TRIG30 11111b = DMA4TRIG31 SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 358: Dmactl3 Register
00000b = DMA6TRIG0 00001b = DMA6TRIG1 00010b = DMA6TRIG2 ⋮ 11110b = DMA6TRIG30 11111b = DMA6TRIG31 DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 359: Dmactl4 Register
DMAABORT is set. 0b = NMI does not interrupt DMA transfer 1b = NMI interrupts a DMA transfer SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 360: Dmaxctl Register
0b = Edge sensitive (rising edge) 1b = Level sensitive (high level) DMAEN DMA enable 0b = Disabled 1b = Enabled DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 361 1b = DMA transfer interrupted by NMI DMAREQ DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0b = No DMA start 1b = Start DMA SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 362: Dmaxsa Register
Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxSA with word instructions, bits 19-16 are cleared. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 363: Dmaxda Register
Reading or writing bits 19–16 requires the use of extended instructions. When writing to DMAxDA with word instructions, bits 19–16 are cleared. SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 364: Dmaxsz Register
0001h = One byte or word is transferred. 0002h = Two bytes or words are transferred. ⋮ FFFFh = 65535 bytes or words are transferred. DMA Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 365: Dmaiv Register
0Eh = Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG 10h = Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt Priority: Lowest SLAU367P – October 2012 – Revised April 2020 DMA Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 366: I/O Configuration
Topic Page ..................12.1 Digital I/O Introduction ..................12.2 Digital I/O Operation ....................12.3 I/O Configuration ..................12.4 Digital I/O Registers Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 367 PB, PC, PD, PE, and PF behave similarly. When reading from ports that contain fewer than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 368 PxDIR, PxREN, and PxOUT for proper I/O configuration. Table 12-1. I/O Configuration PxDIR PxREN PxOUT I/O Configuration Input Input with pulldown resistor Input with pullup resistor Output Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 369: I/O Function Selection
PxIE bit and the GIE bit are set. Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt. • Bit = 0: No interrupt is pending • Bit = 1: An interrupt is pending SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 370 ; Task starts here RETI ; Back to main program P1_1_HND ; Vector 4: Port 1 bit 1 ; Task starts here Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 371 2. Clear LOCKLPM5 3. If not wake-up from LPMx.5: clear all PxIFGs to avoid erroneous port interrupts 4. Enable port interrupts in PxIE SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 372 All other port configuration register settings such as PxDIR, PxREN, PxOUT, PxIES, and PxIE contents are lost. Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 373 NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG flags are set, and it cannot be determined which port caused the I/O wakeup. SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 374: 12.4 Digital I/O Registers
Port 1 Select 1 Read/write Byte Section 12.4.7 or PASEL1_L P1SELC Port 1 Complement Selection Read/write Byte Section 12.4.8 or PASELC_L Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 375 Port 1 Interrupt Enable Read/write Byte Section 12.4.10 or PAIE_L P1IFG Port 1 Interrupt Flag Read/write Byte Section 12.4.11 or PAIFG_L SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 376 Port 3 Interrupt Enable Read/write Byte Section 12.4.10 or PBIE_L P3IFG Port 3 Interrupt Flag Read/write Byte Section 12.4.11 or PBIFG_L Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 377 Port 5 Interrupt Enable Read/write Byte Section 12.4.10 or PCIE_L P5IFG Port 5 Interrupt Flag Read/write Byte Section 12.4.11 or PCIFG_L SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 378 Port 7 Interrupt Enable Read/write Byte Section 12.4.10 or PDIE_L P7IFG Port 7 Interrupt Flag Read/write Byte Section 12.4.11 or PDIFG_L Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 379 Port 9 Interrupt Enable Read/write Byte Section 12.4.10 or PEIE_L P9IFG Port 9 Interrupt Flag Read/write Byte Section 12.4.11 or PEIFG_L SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 380 Port 11 Interrupt Enable Read/write Byte Section 12.4.10 or PFIE_L P11IFG Port 11 Interrupt Flag Read/write Byte Section 12.4.11 or PFIFG_L Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 381 0000h PAIE_L Read/write Byte PAIE_H Read/write Byte PAIFG Port A Interrupt Flag Read/write Word 0000h PAIFG_L Read/write Byte PAIFG_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 382 0000h PBIE_L Read/write Byte PBIE_H Read/write Byte PBIFG Port B Interrupt Flag Read/write Word 0000h PBIFG_L Read/write Byte PBIFG_H Read/write Byte Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 383 0000h PCIE_L Read/write Byte PCIE_H Read/write Byte PCIFG Port C Interrupt Flag Read/write Word 0000h PCIFG_L Read/write Byte PCIFG_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 384 0000h PDIE_L Read/write Byte PDIE_H Read/write Byte PDIFG Port D Interrupt Flag Read/write Word 0000h PDIFG_L Read/write Byte PDIFG_H Read/write Byte Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 385 0000h PEIE_L Read/write Byte PEIE_H Read/write Byte PEIFG Port E Interrupt Flag Read/write Word 0000h PEIFG_L Read/write Byte PEIFG_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 386 0000h PFIE_L Read/write Byte PFIE_H Read/write Byte PFIFG Port F Interrupt Flag Read/write Word 0000h PFIFG_L Read/write Byte PFIFG_H Read/write Byte Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 387 0000h PJSEL1_L Read/write Byte PJSEL1_H Read/write Byte PJSELC Port J Complement Select Read/write Word 0000h PJSELC_L Read/write Byte PJSELC_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 388: Pxiv Register
0Eh = Interrupt Source: Port x.6 interrupt; Interrupt Flag: PxIFG.6 10h = Interrupt Source: Port x.7 interrupt; Interrupt Flag: PxIFG.7; Interrupt Priority: Lowest Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 389: Pxin Register
Table 12-7. P1DIR Register Description Field Type Reset Description PxDIR Port x direction 0b = Port configured as input 1b = Port configured as output SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 390: Pxren Register
01b = Primary module function is selected 10b = Secondary module function is selected 11b = Tertiary module function is selected Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 391: Pxselc Register
Field Type Reset Description PxIE Port x interrupt enable 0b = Corresponding port interrupt disabled 1b = Corresponding port interrupt enabled SLAU367P – October 2012 – Revised April 2020 Digital I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 392: Pxifg Register
Field Type Reset Description PxIFG Undefined Port x interrupt flag 0b = No interrupt is pending. 1b = Interrupt is pending. Digital I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 393 This chapter describes the functionality of the Capacitive Touch I/Os and related control..........................Topic Page ..............13.1 Capacitive Touch I/O Introduction ................13.2 Capacitive Touch I/O Operation ..................13.3 CapTouch Registers SLAU367P – October 2012 – Revised April 2020 Capacitive Touch I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 394: Capacitive Touch I/O Principle
DVSS DVCC Direction Control PxOUT.y Output Signal Px.y Cap. Input Signal Capacitive Touch Signal Figure 13-1. Capacitive Touch I/O Principle Capacitive Touch I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 395: Capacitive Touch I/O Block Diagram
It is possible to scan to successive port pins by incrementing the low byte of the Capacitive Touch I/O control register CAPTIOCTL_L by 2. SLAU367P – October 2012 – Revised April 2020 Capacitive Touch I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 396: Captouch Registers
Reset Section CAPTIOxCTL Capacitive Touch I/O x control register Read/write Word 0000h Section 13.3.1 CAPTIOxCTL_L Read/write Byte CAPTIOxCTL_H Read/write Byte Capacitive Touch I/O SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 397: Captioxctl Register
011b = Px.3 100b = Px.4 101b = Px.5 110b = Px.6 111b = Px.7 Reserved Reserved. Always reads 0. SLAU367P – October 2012 – Revised April 2020 Capacitive Touch I/O Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 398 It supports key lengths of 128 bits, 192 bits, and 256 bits. This chapter describes the AES256 accelerator..........................Topic Page ................14.1 AES Accelerator Introduction ................14.2 AES Accelerator Operation ................14.3 AES Accelerator Registers AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 399: Aes Accelerator Block Diagram
AESAXDIN AESAKEY 128-bit 256-bit AES State AES Key Encryption and Decyption Memory Memory Core AESADOUT Figure 14-1. AES Accelerator Block Diagram SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 400: Aes State Array Input And Output
However, it is possible to write one of the registers using byte access and another using word access. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 401 When writing to AESAXDIN, the corresponding byte or word is XORed with the current byte or word of the state. If AESAXDIN is used to write the last byte or word of the state, encryption or decryption starts automatically. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 402 The AES module's encrypt or decrypt operations are triggered if the state was completely written in the AESADIN or AESAXDIN registers. Alternatively, the bit AESDINWR can be set to trigger an operation if AESCMEN = 0. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 403: Aes Encryption Process For 128-Bit Key
AESDINWR flag triggers the next encryption, and the module starts the encryption using the output data from the previous encryption as the input data. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 404: Aes Decryption Process Using Aesopx = 01 For 128-Bit Key
AESADIN after the results of the operation on the previous data were read from AESADOUT. When additional 16 data bytes are written, the module automatically starts the decryption using the key loaded in step 2. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 405: Aes Decryption Process Using Aesopx = 10 And 11 For 128-Bit Key
5. See Section 14.2.6 for instructions on the decryption steps, starting from step 3 (load data). SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 406 AESADIN. Because the AES modules generates a trigger for each word or byte the single transfer mode of the DMA must be used. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 407: Aes Trigger 0-2' Operation When Aescmen
DMA_B, and DMA_C do not play any role but static DMA priorities must be enabled. The DMA triggers must be configured as level-sensitive triggers. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 408: Ecb Encryption
DMA1: Triggered by AES trigger 1, Source: plaintext, Destination: AESADIN, Size: num_blocks*8 words, Single Transfer mode Start encryption: AESBLKCNT= num_blocks; End of encryption: DMA0IFG=1 AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 409: Ecb Decryption
DMA1: Triggered by AES trigger 1, Source: ciphertext, Destination: AESADIN, Size: num_blocks*8 words, Single Transfer mode Start decryption: AESBLKCNT= num_blocks; End of decryption: DMA0IFG=1 SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 410: Cbc Encryption
DMA1: Triggered by AES trigger 1, Source: plaintext, Destination: AESAXDIN, Size: num_blocks*8 words, Single Transfer mode Start encryption: AESBLKCNT= num_blocks; End of encryption: DMA0IFG=1 AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 411: Cbc Decryption
Wait until first block is decrypted: DMA0IFG=1; Setup DMA0 for further blocks: DMA0: // Write previous cipher text into AES module Triggered by AES trigger 0, SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 412 AES Accelerator Operation www.ti.com Source: ciphertext, Destination: AESAXIN, Size: (num_blocks-1)*8 words, Single Transfer mode End of decryption: DMA1IFG=1 AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 413: Ofb Encryption
Source: plaintext, Destination: AESAXDIN, Size: num_blocks*8 words, Single Transfer mode Start encryption: AESBLKCNT= num_blocks; Trigger encryption by setting AESDINWR= 1; End of encryption: DMA1IFG=1 SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 414: Ofb Decryption
Source: ciphertext, Destination: AESAXDIN, Size: num_blocks*8 words, Single Transfer mode Start decryption: AESBLKCNT= num_blocks; Trigger decryption by setting AESDINWR= 1; End of decryption: DMA1IFG=1 AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 415: Cfb Encryption
Destination: ciphertext, Size: num_blocks*8 words, Single Transfer mode Start encryption: AESBLKCNT= num_blocks; Trigger encryption by setting AESDINWR= 1; End of encryption: DMA1IFG=1 SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 416: Cfb Decryption
Source: ciphertext, Destination: AESADIN, Size: num_blocks*8 words, Single Transfer mode Start decryption: AESBLKCNT= num_blocks; Trigger decryption by setting AESDINWR= 1; End of decryption: DMA1IFG=1 AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 417: Aes256 Registers
AES accelerator XORed data in register Write only Word Section 14.3.7 AESAXIN AES accelerator XORed data in register Write only Word Section 14.3.8 (no trigger) SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 418: Aesactl0 Register
01b = AES192. The key size is 192 bit. 10b = AES256. The key size is 256 bit. 11b = Reserved AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 419 10b = Generate first round key required for decryption. 11b = Decryption. The provided key is the first round key required for decryption. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 420: Aesactl1 Register
The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 421: Aesastat Register
1 = All bytes written AESBUSY AES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 422: Aesakey Register
AESAKEY_L is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 423: Aesadin Register
AES data in byte n when AESADIN is written as word. AES next data in byte when AESADIN_L is written as byte. Do not mix word and byte access. Always reads as zero. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 424: Aesadout Register
AES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT_L is read as byte. Do not mix word and byte access. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 425: Aesaxdin Register
AES data in byte n when AESAXDIN is written as word. AES next data in byte when AESAXDIN_L is written as byte. Do not mix word and byte access. Always reads as zero. SLAU367P – October 2012 – Revised April 2020 AES256 Accelerator Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 426: Aesaxin Register
AES data in byte n when AESAXIN is written as word. AES next data in byte when AESAXIN_L is written as byte. Do not mix word and byte access. Always reads as zero. AES256 Accelerator SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 427 Cyclic Redundancy Check (CRC) Module Introduction ................15.2 CRC Standard and Bit Order ................15.3 CRC Checksum Generation ....................15.4 CRC Registers SLAU367P – October 2012 – Revised April 2020 CRC Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 428: Lfsr Implementation Of Crc-Ccitt Standard, Bit 0 Is The Msb Of The Result
(bit 0 is the MSB). The fact that bit 0 is treated for some as LSB, and for others as MSB, continues to cause confusion. The CRC16 module therefore provides a bit reversed register pair for CRC16 operations to support both conventions. CRC Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 429 If the checksum itself (with reversed bit order) is included into the CRC operation (as data written to CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero. SLAU367P – October 2012 – Revised April 2020 CRC Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 430: Implementation Of Crc-Ccitt Using The Crcdi And Crcinires Registers
The details of the implemented CRC algorithm are shown by the data sequences in Example 15-2 using word or byte accesses and the CRC data-in as well as the CRC data-in reverse byte registers. CRC Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 431 #039h, &CRCDIRB_L ; "9" #029B1h,&CRCINIRES ; compare result ; CRCRESR contains 08D94h &Success ; no error &Error ; to error handler SLAU367P – October 2012 – Revised April 2020 CRC Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 432: Crc Registers
Read/write Byte CRCINIRES_H Read/write Byte CRCRESR CRC Result Reverse Read only Word FFFFh Section 15.4.4 CRCRESR_L Read/write Byte CRCRESR_H Read/write Byte CRC Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 433: Crcdi Register
CRCINIRES and CRCRESR registers according to the CRC-CCITT standard. Reading the register returns the register CRCDI content. SLAU367P – October 2012 – Revised April 2020 CRC Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 434: Crcinires Register
CRC-CCITT standard). The order of bits is reverse (for example, CRCINIRES[15] = CRCRESR[0]) to the order of bits in the CRCINIRES register (see example code). CRC Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 435 ........................... Topic Page ........16.1 Cyclic Redundancy Check (CRC32) Module Introduction ................16.2 CRC Checksum Generation ................16.3 CRC32 Register Descriptions SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 436: Lfsr Implementation Of Crc-Ccitt As Defined In Standard (Bit 0 Is Msb)
The checksum is stored in the product's memory and is used to check the correctness of the CRC operation result. CRC32 Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 437 &CRCINIRES ; Result = 0? CRC_ERROR ; No, CRCRES <> 0: error ; Yes, CRCRES=0: ; information ok. ; Restore registers SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 438 #039h, &CRCDIRB_L ; "9" cmp #029B1h,&CRCINIRES ; compare result ; CRCRESR contains 08D94h jeq Success ; no error br &Error ; to error handler CRC32 Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 439: Crc32 Registers
CRC16INIRESB1 byte 0018h CRC16INIRESB0 byte 001Eh CRC16RESRW0 CRC16 Result Reverse read/write word FFFFh Section 16.3.1.12 001Fh CRC16RESRB0 byte 001Eh CRC16RESRB1 byte SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 440: Crc32Diw0 Register
CRC32 data in word 1. Data written to the CRC32DILW1 register is included to the present signature in the CRC32INIRES register according to the CRC32- ISO3309 standard. CRC32 Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 441: Crc32Dirbw0 Register
CRC32 data in word1 as bit reversed pattern. Data written to the CRC32DIRBW1 register is included to the present signature in the CRC32INIRES register according to the CRC32-ISO3309 standard. SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 442: Crc32Iniresw0 Register
CRC calculation according to the CRC32- ISO3309 standard. Reading this register returns the current result of the CRC calculation. CRC32 Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 443: Crc32Resrw0 Register
CRC32 result (according to the CRC32-ISO3309 standard). The order of bits is reverse to the order of bits in the CRC32INIRESW0 register. SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 444: Crc16Diw0 Register
CRC16INIRES and CRC16RESR registers according to the CRC-CCITT standard. Reading the register returns the register CRC16DI content. CRC32 Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 445: Crc16Iniresw0 Register
CRC16 reverse result. This register holds the current CRC16 result (according to the CRC16-CCITT standard). The order of bits is reverse to the order of bits in the CRC16INIRESW0 register. SLAU367P – October 2012 – Revised April 2020 CRC32 Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 446 This chapter introduces the LEA..........................Topic Page ....................17.1 LEA Introduction ....................17.2 LEA Operation ....................17.3 LEA Registers Low-Energy Accelerator (LEA) for Signal Processing SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 447: Lea System Block Diagram
(RAM). See the device-specific data sheet for details about LEA availability and LEA data memory size. SLAU367P – October 2012 – Revised April 2020 Low-Energy Accelerator (LEA) for Signal Processing Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 448: Lea Command Groups
4. When the algorithm is complete, another DMA channel transfers the result of that algorithm to the SPI. 5. The SPI transfers the data to an external device. Low-Energy Accelerator (LEA) for Signal Processing SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 449: Dsp Library And Mspware Versions For The Lea
Digital Signal Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports. SLAU367P – October 2012 – Revised April 2020 Low-Energy Accelerator (LEA) for Signal Processing Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 450 This chapter describes the operation of the USS and the USS_A module..........................Topic Page ..................... 18.1 Introduction ................18.2 Operation of the USS Module ....................18.3 Debug Features Ultrasonic Sensing Solution (USS, USS_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 451 In ultra low power bias mode the ASQ sequencer performs an extended power sequence dedicated for the ultra low power utility meter market. SLAU367P – October 2012 – Revised April 2020 Ultrasonic Sensing Solution (USS, USS_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 452: Uss And Uss_A Block Diagram
UUPS • HSPLL • SAPH or SAPH_A • SDHS Figure 18-2 shows control signals that connect the submodules. Ultrasonic Sensing Solution (USS, USS_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 453: Uss And Uss_A Submodule Connections
(start measurement) Example 2: ASQ_ACQTRG: The signal is from ASQ to tell the receiver submodule to ACQTRG (acquisition trigger). SLAU367P – October 2012 – Revised April 2020 Ultrasonic Sensing Solution (USS, USS_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 454: Auto Mode And Register Mode
In auto mode, the entire measurement sequence is executed by the PSQ and the ASQ. The start-up sequence is simple but the following order must be used: Ultrasonic Sensing Solution (USS, USS_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 455: Uss_Pwrreq Signal Source
(SAPHATM_A to SAPHATM_F). • ASQ_PPGTRG: ASQ to PPG to generate excitation pules. SLAU367P – October 2012 – Revised April 2020 Ultrasonic Sensing Solution (USS, USS_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 456: Control Signals Among Uss Submodules
UUPSCTL.UPSTATE = 3 UUPSCTL.USSPWRDN = 1, Stop the current measurement PSQ_STOP UUPSCTL.USSSTOP = 1 or Enter immediately debug mode Ultrasonic Sensing Solution (USS, USS_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 457 The debugger can read or write any USS registers, but SDHSCTL4.SDHSON and SDHSCTL5.SSTART are not functional. The PSQ ignores the USS_PWRREQ signal. SLAU367P – October 2012 – Revised April 2020 Ultrasonic Sensing Solution (USS, USS_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 458 19.4 Interface to the ASQ (Acquisition Sequencer) ......................19.5 Interrupts ..................... 19.6 Debug Mode ....................19.7 UUPS Registers Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 459: Uss/Uss_A Block Diagram
BIAS_REF block: Generates required reference voltages and currents for the SDHS, HSPLL, and USS LDO. • USS_LDO block: Generates regulated 1.6 V, which is used by the USS submodules. SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 460: Uups Block Diagram
8. The PSQ sets UUPSCTL.UPSTATE = 3 to indicate that the USS is fully powered and ready to start a Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 461: Uss Power State
Note: A time-out should not happen during normal operating conditions. Make sure that the USSXT oscillator is enabled and working properly. SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 462: Uss Power State Control Flow
PLL operation while the system is still settling. Depending on the transducers and other external circuits some considerable power savings can be achieved. Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 463: Uss Power Control
19-4). The ASQ can be triggered by user software by writing SAPHASQTRIG.ASQTRIG = 1 when SAPHASCTL0.TRIGSEL = 0. SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 464: Asq Trigger
UUPSCTL.USSPWRDN bit is cleared when the power down request has been completed. If this bit is set to 1 when the USS module is powered off (OFF state), it is cleared immediately. Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 465: Power States After Measurement Completion
The SDHS is sampling data (SDHSCTL5.SDHS_LCK = 1) even when the measurement is not under ASQ control (register mode). SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 466 Clear UUPSCTL.USS_BUSY bit to zero upon receiving the ASQ_ACQDONE from the ASQ. • Ignore the USS_PWRREQ signal (writing 1 to UUPSCTL.USSPWRUP in debug mode has no effect). Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 467: 19.7 Uups Registers
Section 19.7.7 UUPSDESCHI UUPS Descriptor Register H. read-only BA10h Section 19.7.8 UUPSCTL UUPS Control read-write 800h Section 19.7.9 SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 468: Uupsiidx Register
2h (R) = Interrupt Source: PREQIG 3h (R) = Interrupt Source: STPBYDB 4h (R) = Reserved; Interrupt Priority: Lowest RESERVED Reserved Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 469: Uupsmis Register
UUPS Power Up Time Out Masked Interrupt Status bit. Reset type: PUC 0h (R) = No interrupt pending 1h (R) = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 470: Uupsris Register
0h (R) = Time out during power up has not occurred 1h (R) = Time out during power up has occurred Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 471: Uupsimsc Register
0h (R/W) = UUPS Power Up Time Out Interrupt is disabled. 1h (R/W) = UUPS Power Up Time Out Interrupt is enabled. SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 472: Uupsicr Register
Power Request Ignored Interrupt Clear bit. Write 1 to Clear RIS.PREQIG bit PTMOUT UUPS Power Up Time Out Interrupt Clear bit. Write 1 to clear RIS.PTMOUT bit. Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 473: Uupsisr Register
PTMOUT UUPS Power Up Time Out Interrupt Set bit. Write 1 to set RIS.PTMOUT bit Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 474: Uupsdesclo Register
RTL for modules that can have multiple instances MAJREV Major Revision Reset type: PUC MINREV Minor Revision Reset type: PUC Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 475: Uupsdeschi Register
Table 19-15. UUPSDESCHI Register Field Descriptions Field Type Reset Description 15-0 MODULEID BA10h Module Identifier. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 476: Uupsctl Register
2h (R/W) = Ext. trigger (see the device-specific data sheet) 3h (R/W) = Ext. trigger (see the device-specific data sheet) Universal USS Power Supply (UUPS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 477 0h (R) = USS LDO is powered down or in transition state 1h (R) = USS LDO is powered on SLAU367P – October 2012 – Revised April 2020 Universal USS Power Supply (UUPS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 478 20.3 PLL Control (CTL) Register ............20.4 Start-up Sequence of the USSXT Oscillator ......................20.5 Interrupts ....................20.6 HSPLL Registers High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 479: Uss Or Uss_A Block Diagram
OSCTYPE OSCEN PLL_CLK USSXTIN (68 to 80 MHz) ½ USSXTOUT HSPLLUSSXTLCTL. USSXT_BOUT HSPLLCTL. OSCSTATE PLL_LOCK Figure 20-2. HSPLL Block Diagram SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 480 USSXT_BOUT pin can be monitored or used as a clock source. Never use the USSXTOUT pin for monitoring or for a clock source. High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 481 5. Now the USSXT is running. The USS module can be powered up. NOTE: All of the USS submodules must be configured properly before powering up the USS module. SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 482 The HSPLL module supports one interrupt: • PLLUNLOCK interrupt: When the PLL output status changes from locked to unlocked, HSPLLRIS.PLLUNLOCK is set to 1. High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 483: Hspll Registers
BD10h Section 20.6.8 HSPLLCTL HSPLL Control Register read-write 4000h Section 20.6.9 HSPLLUSSXTLCTL USSXT Control Register read-write 100h Section 20.6.10 SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 484: Hsplliidx Register
0h (R) = No Interrupt pending 1h (R) = Interrupt Source: PLLUNLOCK; Interrupt Priority: Highest 2h (R) = Reserved; Interrupt Priority: Lowest RESERVED Reserved High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 485: Hspllmis Register
HSPLL Unlock Masked Interrupt Status bit. Reset type: PUC 0h (R) = No interrupt pending 1h (R) = Interrupt pending SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 486: Hspllris Register
0h (R) = PLL status has not been changed 1h (R) = PLL status has been changed from Lock to Unlock High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 487: Hspllimsc Register
PLL Unlock Interrupt Mask bit. Reset type: PUC 0h (R/W) = PLL Unlock Interrupt is disabled 1h (R/W) = PLL Unlock Interrupt is enabled SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 488: Hspllicr Register
Reset Description 15-1 RESERVED Reserved PLLUNLOCK PLL Unlock Interrupt Clear bit. Write 1 to clear RIS.PLLUNLOCK bit Reset type: PUC High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 489: Hspllisr Register
Reset Description 15-1 RESERVED Reserved PLLUNLOCK PLL Unlock Interrupt Set bit. Write 1 to set RIS.PLLUNLOCK bit Reset type: PUC SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 490: Hsplldesclo Register
RTL for modules that can have multiple instances MAJREV Major Revision Reset type: PUC MINREV Minor Revision Reset type: PUC High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 491: Hsplldeschi Register
MODULEID R-BD10h Table 20-9. HSPLLDESCHI Register Field Descriptions Field Type Reset Description 15-0 MODULEID BD10h Module Identifier. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 492: Hspllctl Register
0h (R/W) = Input frequency is equal to 6MHz or lower than 6MHz 1h (R/W) = Input frequency is higher than 6MHz RESERVED Reserved High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 493 Reset type: PUC 0h (R) = PLL is not running or not locked 1h (R) = PLL is locked SLAU367P – October 2012 – Revised April 2020 High-Speed PLL (HSPLL) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 494: Hspllussxtlctl Register
USSXTEN USSXT Enable. Reset type: PUC 0h (R) = Disable USSXT Oscillator 1h (R) = Enable USSXT Oscillator High-Speed PLL (HSPLL) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 495 Interrupts Triggers ....................21.7 DMA Triggers ................21.8 SAPH and SAPH_A Registers SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 496 Writing any other value to the KEY register locks the registers. Read accesses are always allowed. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 497: Uss Or Uss_A Block Diagram
SAPHPGCTL. PLL CLK Counters PGSEL Figure 21-2. PPG or PPG_A Block Diagram SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 498: Ppg Or Ppg_A Internal State Diagrams For Single Tone
PPG_A Figure 21-3. PPG or PPG_A Internal State Diagrams for Single Tone Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 499 1 to SAPH_APGCTL.STOP. The PPG_A immediately stops generating pulses. The SAPH_APGCTL.STOP bit is automatically cleared to zero. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 500: Ppg_A State Diagram For Dual Tone
XMOD = 2 by directly writing or using the DMA, the PPG_A automatically stops when it completes Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 501: Ppg_A State Diagram For Trill Tone
SAPH_APGC.PLEV and SAPH_APGC.PHIZ bits. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 502: Ppg_A Software Flow Chart For Multi Tone
Figure 21-11. PPG_A Multi Tone Generation With SAPHPGC.PPOL = 1 (Starts With Low Polarity) Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 503 SAPHPCG.SPULSE are ignored. To terminate the PPG test tone generation, write SAPHPGCTL.TONE = 0. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 504: Phy Output Pins
PPG are output on the selected pin. This is the typical use case for the flow measurement application. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 505: Trim Registers
The trim registers are locked when SAPHTACTL.UNLOCK = 0. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 506: Saph Or Saph_A Analog Input Signal Chain
(shorter ringing). Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 507: Before Excitation
The pulses are driven to the transducer 0 (TR0) (see Figure 21-15). SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 508 GND through the SWG1 switch (see Figure 21-16 Figure 21-12). Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 509: Before Reception
CH1_OUT is connected to GND through the SWG1 switch (see Figure 21-17). SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 510 ASQ control is possible for various signal chain elements. In ultra low power bias mode all control is obtained by the ASQ. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 511: Asq Block Diagram
ASQ is actively controlling the measurement sequences, because these changes interfere with the measurement timings. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 512: Time Mark Events
ASQ registers, write SAPHASCTL0.ASQTEN = 1 before triggering the ASQ. The SAPHASCTL0.ASQTEN bit must be set before triggering the ASQ. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 513: Auto Mode And Register Mode
The order of the time mark events is determined by the counter values written to the SAPHATM_x registers. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 514: Auto Mode And Register Mode Example
At (e), the sequence is completed. The interrupt service routine perform calculations and sets the system to LPMx again. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 515: Ultra-Low-Power Bias Mode Example
S_Pulse to X-Pulse and when the PPG_A state machine transitions from X-Pulse to S- Pulse. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 516: Saph Registers
Section SAPH_APGLPER 21.8.24 SAPHPGHPER Pulse Generator High Period read-write Section SAPH_APGHPER 21.8.25 Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 517 Section APH_AATIMLO 21.8.44 SAPHATIMHI Acquisition Timer High Part read-only Section SAPH_AATIMHI 21.8.45 SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 518: Saphiidx/Saph_Aiidx Register
The interrupt indicates that one measurement has been completed. RESERVED Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 519: Saphmis/Saph_Amis Register
This interrupt indicates that either WINHI interrupt or WINLO interrupt has occurred in SDHS. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 520: Saphris/Saph_Aris Register
This interrupt indicates that either WINHI interrupt or WINLO interrupt has occurred in SDHS. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 521: Saphimsc/Saph_Aimsc Register
Reset type: PUC DATAERR This bit enables the DATAERR interrupt. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 522: Saphicr/Saph_Aicr Register
Writing one this bit to clear the pending DATAERR interrupt. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 523: Saphisr/Saph_Aisr Register
Writing one this bit generates a DATAERR interrupt by software. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 524: Saphdesclo/Saph_Adesclo Register
Feature Version 11-8 INSTNUM Instance Number MAJREV Major Revision MINREV Minor Revision Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 525: Saphdeschi/Saph_Adeschi Register
Table 21-13. SAPHDESCHI/SAPH_ADESCHI Register Field Descriptions Field Type Reset Description 15-0 ModuleID 5553h SAPH's Identifier SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 526: Saphkey/Saph_Akey Register
Note: This register is write only. Reading always returns with zero. 454Bh (W) = 0x454B Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 527: Saphoctl0/Saph_Aoctl0 Register
0h (R/W) = Ch0 Output is HiZ 1h (R/W) = CH0 Output is driving SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 528: Saphoctl1/Saph_Aoctl1 Register
SAPHOCTL0.CH0OE 1h (R/W) = CH0 Output is set low with termination strength Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 529: Saphosel/Saph_Aosel Register
3h (R/W) = CH0_OUT is used as a GPO pin. It is controlled by SAPHOCTL0.CH0OUT and SAPHOCTL0.CH0OE. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 530: Saphch0Put/Saph_Ach0Put Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTL.UNLOCK=0 during normal operation. Reset type: BOR Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 531: Saphch0Pdt/Saph_Ach0Pdt Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTL.UNLOCK=0 during normal operation. Reset type: BOR SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 532: Saphch0Tt/Saph_Ach0Tt Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTL.UNLOCK=0 during normal operation. Reset type: BOR Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 533: Saphch1Put/Saph_Ach1Put Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTL.UNLOCK=0 during normal operation. Reset type: BOR SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 534: Saphch1Pdt/Saph_Ach1Pdt Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTL.UNLOCK=0 during normal operation. Reset type: BOR Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 535: Saphch1Tt/Saph_Ach1Tt Register
SAPHTACTL.UNLOCK=1. For secure the trim value, it is recommended to keep SAPHTACTLUNLOCK=0 during normal operation. Reset type: BOR SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 536: Saphmcnf/Saph_Amcnf Register
3h (R/W) = Buffer impedance 2950 Ohms for RxBias and 2900 Ohms for TxBias Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 537: Saphtactl/Saph_Atactl Register
When UNLOCK = 1, the trim registers are allowed to be updated (SAPHCH0PUT, SAPHCH0PDT, SAPHCH0TT, SAPHCH1PUT, SAPHCH1PDT, and SAPHCH1TT). Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 538: Saphictl0/Saph_Aictl0 Register
1h (R/W) = The input multiplexer is controlled by ASQ (auto mode) Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 539 Eh (R/W) = no channel is selected Fh (R/W) = no channel is selected SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 540: Saphbctl/Saph_Abctl Register
0h (R/W) = Rx bias switch is open. 1h (R/W) = Rx bias switch is closed (enabled). Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 541 SAPHBCTL.CH1EBSW, SAPHBCTL.PGABSW bits (register mode). 1h (R/W) = Bias switches are controlled by ASQ (auto mode) SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 542: Saphpgc/Saph_Apgc Register
Excitation Pulse Count. This bit field defines the number of excitation pulses. Minimum value is zero. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 543: Saphpglper/Saph_Apglper Register
The minimum count is two regardless of the value set in this register. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 544: Saphpghper/Saph_Apghper Register
The minimum count is two regardless of the value set in this register. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 545: Saphpgctl/Saph_Apgctl Register
0h (R/W) = CH0 is selected 1h (R/W) = CH1 is selected SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 546 1h (R/W) = PPG output channel is selected by ASQ (auto mode). Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 547: Saphppgtrig/Saph_Appgtrig Register
SAPHPGCTL.TRSEL =0. Note: This bit is write only. Reading always returns with zero. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 548: Saph_Axpgctl Register
Any other number will generate up the number of excitation pulses set by this field . Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 549: Saph_Axpglper Register
The minimum count is two regardless of the value set in this register. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 550: Saph_Axpghper Register
The minimum count is two regardless of the value set in this register. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 551: Saphasctl0/Saph_Aasctl0 Register
ASQ. This bit is self cleared. Reset type: PUC RESERVED Reserved SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 552 Note: This bit field is static, does not reflect the currently reamining measurement numbers. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 553: Saphasctl1/Saph_Aasctl1 Register
Read Only bit. This bit indicates the currently selected Tx channel. Reset type: PUC RESERVED RESERVED Reserved RESERVED Reserved SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 554 0h (R/W) = Channel toggle is disabled. 1h (R/W) = Channel toggle is enabled at each PNGDN interrupt. Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 555: Saphasqtrig/Saph_Aasqtrig Register
= 0. Note: This bit is write only. Reading always returns with zero. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 556: Saphapol/Saph_Aapol Register
1 = PPG output pulses starts with logical low polarity. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 557: Saphaplev/Saph_Aaplev Register
PCPHIZ bit 3 = 0. 0 = Logical Low. 1 = Logical High. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 558: Saphaphiz/Saph_Aaphiz Register
0 = PPG ouput level is determined by SAPHAPLEV.PCPLEV bits 1 = Hi-z. regardless of SAPHAPLEV.PCPLEV bits Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 559: Saphatm_A/Saph_Aatm_A Register
Tx bias. The minimum value is two. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 560: Saphatm_B/Saph_Aatm_B Register
B and D is for the SDHS settling time. The minimum value is two. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 561: Saphatm_C/Saph_Aatm_C Register
The time between C and D is for the Rx bias settling time. The minimum value is two. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 562: Saphatm_D/Saph_Aatm_D Register
+ transfer time via DTC. The minimum value is two. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 563: Saphatm_E/Saph_Aatm_E Register
ASQ time counter is reset. The minimum value is two. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 564: Saphatm_F/Saph_Aatm_F Register
Note: TIMEMAR E should be programmed to be longer than TIMEMARK F. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 565: Saphtbctl/Saph_Atbctl Register
ASQ is active. Note: This bit is write only. Reading always returns with zero. SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 566: Saphatimlo/Saph_Aatimlo Register
ASQ Timer Counter low part. The reading this register returns the counter value [15:0]. Reset type: PUC Sequencer for Acquisition, Programmable Pulse Generator, and Physical SLAU367P – October 2012 – Revised April 2020 Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 567: Saphatimhi/Saph_Aatimhi Register
ASQ Timer Counter high part. The reading this register returns the counter value [19:16]. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 568 ..................... 22.1 Introduction ................22.2 SDHS Functional Operation ......................22.3 Interrupts ..................... 22.4 Debug Mode ....................22.5 SDHS Registers Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 569: Uss Block Diagram
(Shared with LEA) CH0_IN Filter CH1_IN Copyright © 2017, Texas Instruments Incorporated Figure 22-1. USS Block Diagram The SDHS module consists of three blocks: the programmable gain amplifier (PGA), the sigma-delta high speed (SDHS), and the data transfer controller (DTC) (see Figure 22-1). -
Page 570: Sdhs Block Diagram
(see Figure 22-3 Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 571: Sigma-Delta Principle
22.2.3.1 CIC Filter Figure 22-4 shows the structure of a CIC filter, which is selected when SDHSCTL1.OSR = 10. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 572: Filter Structure
1.25 1.5 1.75 2.25 2.5 2.75 3.25 3.5 3.75 4.25 4.5 F/Fs Figure 22-5. SDHS Filter Frequency Response, SDHSCTL1.OSR = 10 Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 573: Sdhs Filter Frequency Response Within F
The final frequency response of the SDHS digital filter is determined by SDHSCTL1.OSR bit. Figure 22-8 shows the frequency response of cascading CIC and CIC beyond f (normalized) when SDHSCTL1.OSR = 20. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 574: Sdhs Filter Frequency Response, Sdhsctl1.Osr
, SDHSCTL1.OSR = 20 Figure 22-10 shows the frequency response of cascading CIC and CIC within f (normalized) when SDHSCTL1.OSR = 40. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 575: Sdhsctl1.Osr
, SDHSCTL1.OSR = 80 Figure 22-12 shows the frequency response of cascading CIC and CIC within f (normalized) when SDHSCTL1.OSR = 160. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 576: Sdhsctl1.Osr
SDHSCTL0.SHIFT value is equivalent of multiplying the output data by 2 at every shift. Take care when using SDHSCTL0.SHIFT bits and ensure that signal overflow never happens after shifting. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 577: Bits Selection From Filter To The Data Register (Sdhsctl0.Dalgn = 0)
15 14 13 11 10 SDHSDT Register Figure 22-13. Bits Selection From Filter to the Data Register (SDHSCTL0.DALGN = 0) SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 578: Bits Selection From Filter To The Data Register (Sdhsctl0.Dalgn = 1)
SDHSDT register. Then the DTC reads the data from SDHSDT register and transfers to the destination memory location. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 579 CPU or DMA. If the CPU or DMA attempts to access the same memory, 0x3FFF is returned and an NMI is generated (DACCESSIFG). SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 580: Data Output Path
±1 dB 100110b 10.7 ±1 dB ±1 dB 100111b 11.7 ±1 dB ±1 dB 101000b 12.2 ±1 dB ±1 dB Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 581 ±1 dB 111101b 28.9 ±1 dB ±1 dB 111110b 29.8 ±1 dB ±1 dB 111111b 30.8 ±1 dB ±1 dB SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 582: Sdhs Power And Conversion Trigger Source
Control by: SDHS Power up Conversion Start Register SDHSCTL0.TRGSRC = 0 SDHSCTL4.SDHSON SDHSCTL5.SSTART Auto SDHSCTL0.TRGSRC = 1 ASQ (ASQ_ACQARM signal) ASQ (ASQ_ACQTRIG signal) Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 583: Sdhs Operation In Register Mode (Sdhsctl0.Trgsrc = 0)
3. Turn on the USS module. Figure 22-18 shows an example of USS measurement in auto mode (see for details). SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 584: Sdhs Operation As Part Of Uss Measurement (Sdhsctl0.Trgsrc = 1)
22-19). However, this is not recommended when SDHSCTL0.AUTOSSDIS = 1, because the SDHS may not be fully settled before data conversion starts. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 585 No delay Delay = 4 × system clock period + 4 × (PLL clock period × 10) after the trigger SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 586: Example Using Sdhsctl3.Trigen Bit (Sdhsctl0.Autossdis = 0)
Sample SDHSCTL3.TRIGEN bit SDHSCTL4.SDHSON or ASQ_ACQARM SDHSCTL5.SDHS_LOCK bit (Read Only) Figure 22-19. Example Using SDHSCTL3.TRIGEN Bit (SDHSCTL0.AUTOSSDIS = 0) Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 587: Example Using Sdsctl3.Trigen Bit (Sdhsctl0.Autossdis = 1)
NOTE: In the following sections, it is assumed that SDHSCTL3.TRIGEN is set to 1 before powering up the SDHS. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 588: Conversion Start And Stop When Sdhsctl0.Autossdis
Last Sample SDHSCTL4.SDHSON or ASQ_ACQARM SDHSCTL5.SDHS_LOCK bit (Read Only) Figure 22-21. Conversion Start and Stop When SDHSCTL0.AUTOSSDIS = 0 Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 589: Conversion Start And Stop When Sdhsctl0.Autossdis
INTDLY can be used if the unsettled output data should be skipped. This skipping is not required for most applications. See Table 22-8 for the output data settling time. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 590: Sdhsctl0.Autossdis = 0, Sdhsctl2.Smpctloff = 0, Sdhsctl0.Intdly = 0, Total Sample
(Read Only) Figure 22-24. SDHSCTL0.AUTOSSDIS = 0, SDHSCTL2.SMPCTLOFF = 0, SDHSCTL0.INTDLY = 0, Total Sample Size is Controlled by SDHSCTL2.SMPSZ Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 591: Sdhsctl0.Autossdis = 1, Sdhsctl2.Smpctloff = 0, Sdhsctl0.Intdly = 0, Total Sample
SDHSWINHITH and SDHSWINLOTH registers are in the correct data format. The interrupt flags (WINHI and WINLO) must be reset by user software. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 592: Sdhs Conversion Stop Conditions
Assert Don't care SDHS power Power off Data conversion Stop SDHSRIS.ISTOP No change SDHS_ACQDONE Assert (to ASQ) SDHSRIS.ACQDONE Assert Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 593: Sdhs Response To Conversion Stop Signals When Data Conversion Is Not Running
The ASQ stops the SDHS operation SDHS is not performing data conversion SDHS_ACQDONE (ACQ_SDHSSTOP: 0 → 1) Assert (to ASQ) SDHSRIS.ACQDONE No change SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 594 SDHSCTL5.SSTART bits are prohibited. If the SDHS is already performing data conversion, the data conversion is stopped automatically and the SDHSRIS.ISTOP bit is asserted (see Table 22-9). Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 595: 22.5 Sdhs Registers
22.5.18 SDHSWINLOTH SDHS Window Comparator Low Threshold read-write Section Register. 22.5.19 SDHSDTCDA DTC destination address register read-write Section 22.5.20 SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 596: Sdhsiidx Register
6h (R) = Interrupt Source: SDHSRIS.WINLO 7h (R) = Reserved; Interrupt 8h (R) = Reserved; Interrupt Priority: Lowest Reserved Reserved. Always reads as 0. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 597: Sdhsmis Register
SDHS Data Overflow Masked Interrupt Status bit. Reset type: PUC 0h (R) = No interrupt pending 1h (R) = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 598: Sdhsris Register
0h (R) = No WINHI event 1h (R) = The output data value is higher than the value in the SDHSWINHITH register Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 599 When DTC is disabled (SDHSCTL2.DTCOFF = 1), At least one new sample has been overwritten to SDHSDT register before the previous value is read. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 600: Sdhsimsc Register
SDHS Data Overflow Interrupt Mask bit. Reset type: PUC 0h (R/W) = Interrupt is disabled 1h (R/W) = Interrupt is enabled Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 601: Sdhsicr Register
SDHS Converstion Start Trigger Interrupt Clear bit. ACQDONE Acquisition Done Interrupt Clear bit. SDHS Data Overflow Interrupt Clear bit. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 602: Sdhsisr Register
SDHS Start Conversion Trigger Interrupt Set bit. ACQDONE Acquisition Done Interrupt Set bit. SDHS Data Overflow Interrupt Set bit. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 603: Sdhsdesclo Register
RTL for modules that can have multiple instances MAJREV Major Revision Reset type: PUC MINREV Minor Revision Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 604: Sdhsdeschi Register
R-BB10h Table 22-19. SDHSDESCHI Register Field Descriptions Field Type Reset Description 15-0 MODULEID BB10h Module Identifier. Reset type: PUC Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 605: Sdhsctl0 Register
1h (R/W) = Offset binary 2h (R/W) = Reserved (defaults to 0, 2s complement) 3h (R/W) = Reserved (defaults to 0, 2s complement) SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 606 ASQ controls the measurement sequences) - SHDS_PWR_UP signal to turns on the SDHS - CONVERSION_START signal to start data convesion Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 607: Sdhsctl1 Register
0h (R/W) = 10 1h (R/W) = 20 2h (R/W) = 40 3h (R/W) = 80 4h (R/W) = 160 SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 608: Sdhsctl2 Register
Care must be taken when writing a value to SDHSCTL2.SMPSZ. If SDHSCTL2.SMPSZ - SDHSCTL0.INTDLY + 1 <= 0, then no data output to SDHSDT register. Reset type: PUC Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 609: Sdhsctl3 Register
1h (R/W) = SDHS Trigger is enabled. Once this bit is asserted, SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7,SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA registers are locked (not allowed to be modified). SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 610: Sdhsctl4 Register
Reset type: PUC 0h (R/W) = Power down the SDHS module 1h (R/W) = Power on the SDHS module Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 611: Sdhsctl5 Register
1h (R) = SDHSCTL3 register is locked as well as SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7, SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA registers. Only read is allowed. Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 612 - When SDHSCTL0.TRGSRC = 1, this bit is invalid. Reset type: PUC 0h (R/W) = Stop conversion 1h (R/W) = Start conversion Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 613: Sdhsctl6 Register
PGA Gain Control bits. These bits control the Gain range of the analog amplifier. See PGA Gain Table for details. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 614: Sdhsctl7 Register
71MHz <= Fmod < 74MHz: 0xE 68MHz <= Fmod < 71MHz: 0xF (Reset) Where Fmod = PLL output frequency Reset type: PUC Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 615: Sdhsdt Register Field Descriptions
SDHSDT R-0h Table 22-28. SDHSDT Register Field Descriptions Field Type Reset Description 15-0 SDHSDT Conversion Data. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 616: Sdhswinhith Register
Note: Once the condition is detected, it takes 4 system clock cycles + 4 sampling periods to update SDHSRIS.WINHI due to synchonization requirement. Reset type: PUC Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 617: Sdhswinloth Register
Note: Note: Once the condition is detected, it takes 4 system clock cycles + 4 sampling periods to update RIS.WINLO due to synchonization requirement. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Sigma-Delta High Speed (SDHS) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 618: Sdhsdtcda Register
Note: Care must be taken not to go beyond the available memory address range (specified by the device datasheet). The DTC is able to accesses to the LEA RAM only. Sigma-Delta High Speed (SDHS) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 619 Topic Page ..................... 23.1 MTIF Introduction ....................23.2 MTIF Operation ..................23.3 MTIF Block Diagram ....................23.4 MTIF Registers SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 620: Mtif Use Case
While the MTIF output is enabled, the pulse train is sent to the MTIF output. Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 621: Mtif Pulse Diagram
RTC. With an RTC operated from 32.768 kHz, the MTIF can generate pulse rates from 8 to 1024 pulses per second. SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 622: Pgfs Values
Write to MTIFPGCTL (PCPW = 0x5A, Request update of pulse generator PGUR = 1) PGUR = 1) Enter LPM3 Enter LPM3.5 Optional, when required Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 623: Reading The Pulse Rate
"new_value", "transaction_number", and "transaction_state". Record and update each phase of the transaction. This allows recovery after any reset on the next start-up. SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 624: Mtif Block Diagram
The MTIF module supports one input and one output, which can be on separate pins or on a shared pin, depending on the specific device. Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 625: 23.4 Mtif Registers
Section 23.4.7 MTIFPCSR Pulse Counter Status Register read-write Section 23.4.8 MTIFTPCTL Measurement Test Port Control Register read-write F00h Section 23.4.9 SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 626: Mtifpgcnf Register
PGEN PG sub module enable. This bit enables the PG sub module when set to one Reset type: POR Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 627: Mtifpgkval Register
256 periods of the pulse grid frequency(with password protection as in MTIFPGCNF). MTIFPGCNF.PGEN has to be one to perform a change. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 628: Mtifpgctl Register
0xff (e.g. in the last 4ms of a second with a pulse grid frequency of 256Hz) Reset type: PUC Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 629: Mtifpgsr Register
Pulse K-Count Update Acknowledge. This acknowledges a MTIFPGSR.PKUR 2-3 LFCLK cycles after the K-values have been updated. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 630: Mtifpccnf Register
R/W1S PC sub module enable. This bit enables the PC sub module when set to one Reset type: POR Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 631: Mtifpcr Register
Field Type Reset Description 15-0 Pulse Counter value register. This register returns the count value from the pulse counter. SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 632: Mtifpcctl Register
Pulse Counter Read Request. Set this to request an update of MTIFPCR read register from the actual counter. Reset type: PUC Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 633: Mtifpcsr Register
(MTIFPCCNF.PCEN=0) allows a time shift. The read will then be performed and acknowledged after the clock is reenabled. Reset type: PUC SLAU367P – October 2012 – Revised April 2020 Metering Test Interface (MTIF) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 634: Mtiftpctl Register
Test port output enable. This bit allows to enable the test pulse output when set to one Reset type: POR Metering Test Interface (MTIF) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 635: Slau367P - October 2012 - Revised April 2020
The enhanced watchdog timer, WDT_A, is implemented in all devices..........................Topic Page ..................24.1 WDT_A Introduction ..................... 24.2 WDT_A Operation ..................... 24.3 WDT_A Registers SLAU367P – October 2012 – Revised April 2020 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 636 32-ms reset interval using the SMCLK. The user must set up or halt the WDT_A before the initial reset interval expires. Watchdog Timer (WDT_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 637: Watchdog Timer Block Diagram
WDTIS2 WDTIS1 WDTIS0 X_CLK request Clock SMCLK request Request ACLK request Logic VLOCLK request Figure 24-1. Watchdog Timer Block Diagram SLAU367P – October 2012 – Revised April 2020 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 638 In interval timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced, or can be reset with software. Watchdog Timer (WDT_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 639 ; Change watchdog timer interval MOV #WDTPW+WDTCNTCL+SSEL,&WDTCTL ; Stop the watchdog MOV #WDTPW+WDTHOLD,&WDTCTL ; Change WDT to interval timer mode, clock/8192 interval MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS2+WDTIS0,&WDTCTL SLAU367P – October 2012 – Revised April 2020 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 640 Table 24-1. WDT_A Registers Offset Acronym Register Name Type Access Reset Section WDTCTL Watchdog Timer Control Read/write Word 6904h Section 24.3.1 Watchdog Timer (WDT_A) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 641: Wdtctl Register
110b = Watchdog clock source / 2 (15.625 ms at 32.768 kHz) 111b = Watchdog clock source / 2 (1.95 ms at 32.768 kHz) SLAU367P – October 2012 – Revised April 2020 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 642: Timer_A Registers
Timer_A module..........................Topic Page ..................25.1 Timer_A Introduction .................... 25.2 Timer_A Operation .................... 25.3 Timer_A Registers Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 643 = 0. The suffix n, where n = 0 to 6, represents the specific capture/compare registers associated with the Timer_A instantiation. SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 644: Timer_A Block Diagram
D Set Q Unit4 OUT6 Signal EQU0 Timer Clock Reset OUTMOD Copyright © 2016, Texas Instruments Incorporated Figure 25-1. Timer_A Block Diagram Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 645 TAxCCR0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 646: Up Mode
However, one additional count may occur before the counter rolls to zero. Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 647: Continuous Mode
TAxCCR1b TAxCCR1c TAxCCR0d TAxCCR0b TAxCCR0c 0FFFFh TAxCCR1a TAxCCR1d TAxCCR0a Figure 25-6. Continuous Mode Time Intervals SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 648: Up/Down Mode
When the timer is counting in the up direction and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 649: Output Unit In Up/Down Mode
Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 25-10). SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 650: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TAxCCTLn Second Capture Idle Taken COV = 1 Figure 25-11. Capture Cycle Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 651: Output Modes
The output is reset when the timer counts to the TAxCCRn value. It is set when the timer Reset/Set counts to the TAxCCR0 value. SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 652: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TAIFG TAIFG TAIFG Figure 25-12. Output Example – Timer in Up Mode Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 653: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events Figure 25-13. Output Example – Timer in Continuous Mode SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 654: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TA0CCTL1 ; Set output mode=7 #OUTMOD,&TA0CCTL1 ; Clear unwanted bits Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 655 TAxIV register, TAxCCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TAxCCR2 CCIFG flag generates another interrupt. SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 656 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TA0CCR1 ; Task starts here RETI ; Back to main program Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 657 0000h Section 25.3.4 TAxIV Timer_Ax Interrupt Vector Read only Word 0000h Section 25.3.5 TAxEX0 Timer_Ax Expansion 0 Read/write Word 0000h Section 25.3.6 SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 658: Taxctl Register
Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled TAIFG Timer_A interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 659: Taxr Register
Table 25-5. TAxR Register Description Field Type Reset Description 15-0 TAxR Timer_A register. The TAxR register is the count of Timer_A. SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 660: Taxcctln Register
Output. For output mode 0, this bit directly controls the state of the output. 0b = Output low 1b = Output high Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 661: Capture/Compare Interrupt Flag
0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 662: Taxccrn Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest Timer_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 663: Taxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 SLAU367P – October 2012 – Revised April 2020 Timer_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 664: Timer_B Registers
(see the device-specific data sheet). This chapter describes the operation and use of the Timer_B module..........................Topic Page ..................26.1 Timer_B Introduction .................... 26.2 Timer_B Operation .................... 26.3 Timer_B Registers Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 665 Timer_B TBxCCRn registers are double-buffered and can be grouped. • All Timer_B outputs can be put into a high-impedance state. • The SCCI bit function is not implemented in Timer_B. SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 666: Timer_B Block Diagram
UP/DOWN CCR1 Set TBxCCR6 CCIFG Output D Set Q OUT6 Signal Unit6 EQU0 Timer Clock Reset OUTMOD Figure 26-1. Timer_B Block Diagram Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 667 TBxCL0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 668: Up Mode
If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 669: Continuous Mode
TBxCL1b TBxCL1c TBxCL0d TBxCL0b TBxCL0c TBxR (max) TBxCL1a TBxCL1d TBxCL0a EQU0 Interrupt EQU1 Interrupt Figure 26-6. Continuous Mode Time Intervals SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 670: Up/Down Mode
TBxCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero. Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 671: Output Unit In Up/Down Mode
The input signal level can be read at any time from the CCI bit. Devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals. SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 672: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TBxCCTLn Second Capture Idle Taken COV = 1 Figure 26-11. Capture Cycle Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 673: Tbxcln Load Events
TBxCCRn to TBxCLn when TBxR counts to the old TBxCL0 value or to 0 for up/down mode. New data is transferred from TBxCCRn to TBxCLn when TBxR counts to the old TBxCLn value. SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 674: Compare Latch Operating Modes
The output is reset when the timer counts to the TBxCLn value. It is set when the timer Reset/Set counts to the TBxCL0 value. Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 675: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TBIFG TBIFG TBIFG Figure 26-12. Output Example – Timer in Up Mode SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 676: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set Interrupt Events TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Figure 26-13. Output Example – Timer in Continuous Mode Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 677: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TBCCTLx ; Set output mode=7 #OUTMOD,&TBCCTLx ; Clear unwanted bits SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 678: Capture/Compare Tbxccr0 Interrupt Flag
The latencies are: • Capture/compare block CCR0: 11 cycles • Capture/compare blocks CCR1 to CCR6: 16 cycles • Timer overflow TBIFG: 14 cycles Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 679 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TB0CCR1 ; Task starts here RETI ; Back to main program SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 680 0000h Section 26.3.4 TBxIV Timer_B Interrupt Vector Read only Word 0000h Section 26.3.5 TBxEX0 Timer_B Expansion 0 Read/write Word 0000h Section 26.3.6 Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 681: Tbxctl Register
TBIE Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 682 Table 26-6. TBxCTL Register Description (continued) Field Type Reset Description TBIFG Timer_B interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 683: Tbxr Register
Table 26-7. TBxR Register Description Field Type Reset Description 15-0 TBxR Timer_B register. The TBxR register is the count of Timer_B. SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 684: Tbxcctln Register
CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled Undef Capture/compare input. The selected input signal can be read by this bit. Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 685 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 686: Tbxccrn Register
Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBxCCRn register when a capture is performed. Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 687: Tbxiv Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest SLAU367P – October 2012 – Revised April 2020 Timer_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 688: Tbxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 Timer_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 689: 27.1 Rtc Overview
See the device-specific data sheet. Total adjustment range of offset calibration plus temperature compensation. See the RTC_C chapter for details. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock (RTC) Overview Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 690: Rtc_B Registers
This chapter describes the RTC_B module..........................Topic Page ..............28.1 Real-Time Clock RTC_B Introduction ....................28.2 RTC_B Operation ....................28.3 RTC_B Registers Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 691 Real-time clock initialization Most RTC_B module registers have no initial condition. These registers must be configured by user software before use. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 692: Rtc_B Block Diagram
Calendar RTCYEARH RTCYEARL RTCMON RTCDAY Set_RTCAIFG Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Figure 28-1. RTC_B Block Diagram Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 693 RTCAIE, RTCAIFG, and AE bits before writing initial or new time values to the RTC time registers. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 694 In addition, all flags can be cleared by software. Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 695 ; Vector 6: RTCAIFG Flag ; Task starts here RETI ; Back to main program RT0PSIFG_HND ; Vector 8: RT0PSIFG Flag SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 696 In counter mode (RTCMODE = 0), the calibration logic is disabled. Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 697 If a fault occurs during LPM3.5 and the RTCOFIE was set before entering LPM3.5, a wake-up event is issued. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 698 Real-Time Clock Hour Read/write Byte undefined retained or RTCTIM1_L RTCDOW Real-Time Clock Day of Week Read/write Byte undefined retained or RTCTIM1_H Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 699 BCD2BIN BCD-to-Binary Conversion Register Read/write Word not retained Do not access the RTCYEAR register in byte mode. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 700: Rtcctl0 Register
Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 701: Rtcctl1 Register
00b = Minute changed 01b = Hour changed 10b = Every day at midnight (00:00) 11b = Every day at noon (12:00) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 702: Rtcctl2 Register
00b = No frequency output to RTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 703: Rtcsec Register
Seconds – high digit. Valid values are 0 to 5. Seconds – low digit undefined Seconds – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 704: Rtcmin Register
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 705: Rtchour Register
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 706: Rtcdow Register
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 707: Rtcmon Register
Month – high digit. Valid values are 0 or 1. Month – low digit undefined Month – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 708: Rtcyear Register
Decade. Valid values are 0 to 9. Year – lowest digit undefined Year – lowest digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 709: Rtcamin Register
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 710: Rtcahour Register
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 711: Rtcadow Register
1b = This alarm register is enabled Always reads as 0. Day of week undefined Day of week. Valid values are 0 to 6. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 712: Rtcaday Register
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 713: Rtcps0Ctl Register Description
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 714: Rtcps1Ctl Register Description
Prescale timer 1 interrupt flag. In modules supporting LPMx.5 this interrupt can be used as LPMx.5 wake-up event. 0b = No time event occurred 1b = Time event occurred Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 715: Rtcps0 Register
Figure 28-29. RTCPS1 Register RT1PS Table 28-29. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 716: Rtciv Register
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0Ch = Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG 0Eh = Reserved; Interrupt Priority: Lowest Real-Time Clock B (RTC_B) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 717: Bin2Bcd Register
15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number Write: 16-bit BCD number to be converted SLAU367P – October 2012 – Revised April 2020 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 718 Real-Time Clock (RTC_C) Introduction ....................29.2 RTC_C Operation ........... 29.3 RTC_C Operation - Device-Dependent Features ....................29.4 RTC_C Registers Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 719 Most RTC_C module registers have no initial condition. These registers must be configured by user software before use. Figure 29-1 shows the RTC_C block diagram. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 720: Rtc_C Block Diagram (Rtcmode = 1)
Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Copyright © 2016, Texas Instruments Incorporated Figure 29-1. RTC_C Block Diagram (RTCMODE = 1) Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 721 RTCADAY, RTCAHOUR, and RTCAMIN, the alarm is enabled. When enabled, the RTCAIFG is set when the time count transitions from 06:29:59 to 06:30:00 and the RTCDAY equals 5. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 722 ; Write into RTCCTL0 with correct key in word mode MOV.B #00h, &RTCCTL0_H ; Write incorrect key to lock RTC_C Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 723 32768 Hz, so intervals of 16384 Hz, 8192 Hz, 4096 Hz, 2048 Hz, 1024 Hz, 512 Hz, 256 Hz, or 128 Hz are possible. Setting the RT0PSIE bit enables the interrupt. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 724 ; Vector A: RT0PSIFG ; Task starts here RETI ; Back to main program RT1PSIFG_HND ; Vector C: RT1PSIFG Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 725 RT0PS interrupt triggered by RT0PS – Q1 to Q7 (RT0IPx ≠ 000) is based on the calibrated clock. RT1PS interrupt (RT1PSIFG) and RTC counter interrupt (RTCTEVIFG) are also based on the calibrated clock. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 726 RTCTCMP again when RTCTCRDY is set. Figure 29-2 shows the scheme for real-time clock offset error calibration and temperature compensation. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 727: Rtc_C Offset Error Calibration And Temperature Compensation Scheme
RTCTCMP register. The value written into RTCTCMP in this case would be effective until it is updated again by software. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 728 If a fault occurs during LPM3.5 and the RTCOFIE was set before entering LPM3.5, a wake-up event is issued. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 729: Rtc_C Functional Block Diagram In Counter Mode (Rtcmode = 0)
Set_RTCTEVIFG 16-bit overflow 24-bit overflow 32-bit overflow Figure 29-3. RTC_C Functional Block Diagram in Counter Mode (RTCMODE = 0) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 730 For example, if RTPS0 is being updated, set RTCPS1HOLD = 1, and if RTPS1 is being updated, set RTCHOLD = 1. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 731 The RTCOFIFG bit flags a failure of the 32-kHz crystal oscillator. It's main purpose is to wake-up the CPU from LPM3.5 in case an oscillator failure occurred. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 732 These pins are present only on devices that support this feature of RTC_C. Refer to the device-specific data sheet to determine the availability of this feature. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 733: Rtccapx Pin Configuration
(one per tamper source). When RTCIV is read, the RTCCAPIFG is cleared but not the status flags (CAPEV bits). SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 734 Some bits in this register are retained. See the register description to determine which bits are retained. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 735: Rtc_C Registers
BCD-to-binary conversion BCD2BIN Read/write Word 0000h not retained register Do not access the year register RTCYEAR in byte mode. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 736: Rtc_C Event And Tamper Detection Registers
Word undefined retained RTCCNT3 Real-Time Counter 3 Read/write Byte undefined retained RTCCNT4 Real-Time Counter 4 Read/write Byte undefined retained Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 737: Rtcctl0_L Register
Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 738: Rtcctl0_H Register
Real-time clock key. This register should be written with A5h to unlock RTC_C. A write with a value other than A5h locks the module. A read from this register always returns 96h. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 739: Rtcctl1 Register
Counter Mode (RTCMODE = 0) 00b = 8-bit overflow 01b = 16-bit overflow 10b = 24-bit overflow 11b = 32-bit overflow SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 740: Rtcctl3 Register
+1 ppm (RTCOCALS = 1) or –1 ppm (RTCOCALS = 0) adjustment in frequency. Maximum effective calibration value is ±240 ppm. Excess values written above ±240 ppm are ignored by hardware. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 741: Rtctcmp Register
Excess values written above ±240 ppm are ignored by hardware. Changing the sign-bit by writing to RTCTCMP_H becomes effective only after also writing RTCTCMP_L. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 742: Rtcnt1 Register
Table 29-14. RTCNT4 Register Description Field Type Reset Description RTCNT4 undefined The RTCNT4 register is the count of RTCNT4. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 743: Rtcsec Register
Seconds – high digit (0 to 5) Seconds – low digit undefined Seconds – low digit (0 to 9) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 744: Rtcmin Register
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 745: Rtchour Register
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 746: Rtcdow Register
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 747: Rtcmon Register
Month – high digit (0 or 1) Month – low digit undefined Month – low digit (0 to 9) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 748: Rtcyear Register
Century – low digit (0 to 9) Decade undefined Decade (0 to 9) Year – lowest digit undefined Year – lowest digit (0 to 9) Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 749: Rtcamin Register
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 750: Rtcahour Register
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 751: Rtcadow Register
1b = This alarm register is enabled Always 0 Day of week undefined Day of week (0 to 6) SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 752: Rtcaday Register
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 753: Rtcps0Ctl Register
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 754: Rtcps1Ctl Register
111b = Divide by 256 RT1PSIE Prescale timer 1 interrupt enable 0b = Interrupt not enabled 1b = Interrupt enabled (LPMx.5 wake-up enabled) Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 755 Prescale timer 1 interrupt flag. This interrupt can be used as LPMx.5 wake-up event. 0b = No time event occurred 1b = Time event occurred SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 756: Rtcps0 Register
Figure 29-37. RTCPS1 Register RT1PS Table 29-38. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 757: Rtciv Register
0Ch = Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG 0Eh = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 10h = Reserved ; Interrupt Priority: Lowest SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 758: Bin2Bcd Register
15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number. Write: 16-bit BCD number to be converted. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 759: Rtcsecbakx Register
Seconds – high digit. Valid values are 0 to 5. Seconds – low digit Seconds – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 760: Rtcminbakx Register
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit Minutes – low digit. Valid values are 0 to 9. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 761: Rtchourbakx Register
Hours – high digit. Valid values are 0 to 2. Hours – low digit Hours – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 762: Rtcdaybakx Register
Day of month – low Day of month – low digit. Valid values are 0 to 9. digit Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 763: Rtcmonbakx Register
Month – high digit. Valid values are 0 to 3. Month – low digit Month – low digit. Valid values are 0 to 9. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 764: Rtcyearbakx Register
Decade. Valid values are 0 to 9. Year – lowest digit Year – lowest digit. Valid values are 0 to 9. Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 765: Rtctcctl0 Register
1b = At least one tamper event occurred. Status of individual tamper events can be found from the CAPEV bit in RTCCAPxCTL. SLAU367P – October 2012 – Revised April 2020 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 766: Rtccapxctl Register
CAPEV is cleared by the user. Can only be written as 0. 0b = Tamper event did not occur 1b = Tamper event occurred Real-Time Clock C (RTC_C) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 767 Introduction – UART Mode ..............30.3 eUSCI_A Operation – UART Mode .................. 30.4 eUSCI_A UART Registers SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 768 Independent interrupt capability for receive, transmit, start bit received, and transmit complete Figure 30-1 shows the eUSCI_Ax when configured for UART mode. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 769: Eusci_Ax Block Diagram - Uart Mode (Ucsync = 0)
UCTXADDR UCMODEx UCSPB Figure 30-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 770: Character Format
When an idle line is detected, the UCIDLE bit is set. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 771: Idle-Line Format
The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data is misinterpreted as an address. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 772: Address-Bit Multiprocessor Format
(UCTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 773: Auto Baud-Rate Detection - Break/Synch Sequence
The latter case can be discovered by checking the received data and the UCFE bit. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 774: Uart Vs Irda Data Format
= Wake time from any low-power mode. Zero when the device is in active mode. WAKE Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 775: Receive Error Conditions
UCAxRXBUF to detect this condition. Note that, in this case, the UCRXERR flag is not set. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 776: Glitch Suppression, Eusci_A Receive Not Started
If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud-rate generator is turned off. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 777: Bitclk Baud-Rate Timing With Ucos16
0xff The correct setting of UCBRSx can be found as described in Section 30.3.10. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 778: Bitclk16 Modulation Pattern
Table 30-3. BITCLK16 Modulation Pattern Number of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 779: Brclk /Baud Rate
However it is also possible to look up the correct settings in table with typical crystals (see Table 30-5). SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 780 –0.5 BRCLKs and +0.5 RCLKs, independent of the selected baud- SYNC rate generation mode. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 781: Receive Error
(see the device-specific data sheet). SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 782: Recommended Settings For Typical Crystals And Baud Rates
Assumes a stable clock source for BRCLK with negligible jitter (for example, from a crystal oscillator). Any frequency variation or jitter of the clock source will make the errors worse. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 783 SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 784: Uart State Change Interrupt Flags
UCAxIV. The UCAxIV value is added to the PC to automatically jump to the appropriate routine. The following example is given for eUSCI_A0. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 785 (UCRXERR, UCFE, UCPE, UCOE, and UCBRK) are cleared after the read. Thus these errors might go unnoticed. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 786: 30.4 Eusci_A Uart Registers
It is recommended to access these registers using 16-bit access. If 8-bit access is used, the corresponding bit names must be followed by "_H". Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 787: Ucaxctlw0 Register
0b = Received break characters do not set UCRXIFG. 1b = Received break characters set UCRXIFG. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 788: Ucaxctlw1 Register
01b = Approximately 50 ns 10b = Approximately 100 ns 11b = Approximately 200 ns Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 789: Ucaxbrw Register
Baud-Rate Generation" section shows the modulation pattern. Reserved Reserved UCOS16 Oversampling mode enabled 0b = Disabled 1b = Enabled SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 790: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI_A inactive 1b = eUSCI_A transmitting or receiving Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 791: Ucaxrxbuf Register
UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 792: Ucaxabctl Register
1b = Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 793: Ucaxirctl Register
UCIREN IrDA encoder/decoder enable 0b = IrDA encoder/decoder disabled 1b = IrDA encoder/decoder enabled SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 794: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 795: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCAxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 796: Ucaxiv Register
06h = Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 08h = Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 797 Operation – SPI Mode ..................31.4 eUSCI_A SPI Registers ..................31.5 eUSCI_B SPI Registers SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 798 Slave operation in LPM4 Figure 31-1 shows the eUSCI when configured for SPI mode. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 799: Eusci Block Diagram - Spi Mode
Set UCFE Transmit State Machine Set UCxTXIFG Figure 31-1. eUSCI Block Diagram – SPI Mode SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 800: Ucxste Operation
UCSWRST and avoid any unwanted transitions during operation. Clear UCSWRST. BIC.B #UCSWRST,&UCxCTL1 Enable interrupts (optional) with UCRXIE or UCTXIE. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 801: Eusci Master And External Slave (Ucstem = 0)
The fourth pin is used as output to generate a slave enable signal (UCSTEM = 1). The bit UCSTEM is used to select the corresponding mode. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 802: Eusci Slave And External Master
UCxRXBUF before new data is moved to UCxRXBUF. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 803 Timing for each case is shown in Figure 31-4. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 804: Eusci Spi Timing With Ucmsb
PUC signal or when UCSWRST = 1. UCRXIFG is automatically reset when UCxRXBUF is read. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 805 RETI ; Return RXIFG_ISR ; Vector 2 ; Task starts here RETI ; Return SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 806: 31.4 Eusci_A Spi Registers
Interrupt Flag Read/write Word Section 31.4.7 UCAxIV eUSCI_Ax Interrupt Vector Read Word 0000h Section 31.4.8 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 807: Ucaxctlw0 Register
0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 808: Ucaxbrw Register
Bit clock prescaler setting. / UCBRx BitClock BRCLK If UCBRx = 0, f BitClock BRCLK Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 809: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 810: Ucaxrxbuf Register
UCRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 811: Ucaxtxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 812: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 813: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 814: Ucaxiv Register
Priority: Highest 004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 815: 31.5 Eusci_B Spi Registers
Interrupt Flag Read/write Word Section 31.5.7 UCBxIV eUSCI_Bx Interrupt Vector Read Word 0000h Section 31.5.8 SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 816: Ucbxctlw0 Register
0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 817: Ucbxbrw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 818: Ucbxtxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 819: Ucbxie Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 820: Ucbxiv Register
Priority: Highest 0004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 821 ................32.3 eUSCI_B Operation – I C Mode ..................32.4 eUSCI_B I2C Registers SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 822 Slave receiver START detection for auto wake-up from LPMx modes (not LPM3.5 and LPM4.5) Figure 32-1 shows the eUSCI_B when configured in I C mode. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 823: Eusci_B Block Diagram - I
SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 824: Bus Connection Diagram
SCL clock. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 825: Module Data Transfer
10-bit addressing mode with the eUSCI_B module. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 826: Module 10-Bit Addressing Format
The recommended structure of the interrupt service routine can be found in Example 32-3. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 827 SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 828: Time-Line Legend
C state machine returns to its address-reception state. Figure 32-9 shows the slave transmitter operation. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 829: C Slave Receiver Mode
To avoid loss of data, the UCBxRXBUF must be read before UCTXNACK is set. When the master generates a STOP condition, the UCSTPIFG flag is set. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 830: C Slave 10-Bit Addressing Mode
R/W bit set. This sets the UCSTTIFG flag if it was previously cleared by software, and the eUSCI_B modules switches to transmitter mode with UCTR = 1. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 831 SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 832: C Master Transmitter Mode
START, it must be written into UCBxTXBUF again. Any set UCTXSTT or UCTXSTP is also discarded. Figure 32-12 shows the I C master transmitter operation. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 833 (UCGC=1 if general call) USCI continues as Slave Receiver Figure 32-12. I C Master Transmitter Mode SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 834: I 2 C Master Receiver Mode
C transaction is initiated with setting UCTXSTT = 1. Otherwise, the current transaction might be affected. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 835 UCTXIFG = 1 USCI continues as Slave Transmitter Figure 32-13. I C Master Receiver Mode SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 836: Arbitration Procedure Between Two Master Transmitters
Master 1 sends a repeated START condition and master 2 sends a STOP condition. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 837: Synchronization Of Two I
• eUSCI_B is acting as master and a connected slave drives SCL low. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 838 Transmit Interrupt (see Section 32.3.11.2). 32.3.7.3 Clock Low Time-out SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 839 Software support for up to 2 different slave addresses all sharing one interrupt SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 840 The eUSCI_B has only one interrupt vector that is shared for transmission, reception, and the state change. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 841 C State Change Interrupt Operation Table 32-2 describes the I C state change interrupt flags. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 842: C State Change Interrupt Flags
UCBxIV. The UCBxIV value is added to the PC to automatically jump to the appropriate routine. The example is given for eUSCI0_B. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 843 0x1c: ... // Vector 28: clock low time-out break; case 0x1e: ... // Vector 30: 9th bit break; default: break; SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 844 Word 0002h Section 32.4.16 UCBxIV eUSCI_Bx Interrupt Vector Read Word 0000h Section 32.4.17 SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 845: Ucbxctlw0 Register
0b = Do not acknowledge the slave address 1b = Acknowledge the slave address SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 846 0b = Disabled. eUSCI_B released for operation. 1b = Enabled. eUSCI_B logic held in reset state. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 847: Ucbxctlw1 Register
UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold. 11b = Reserved SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 848 00b = 50 ns 01b = 25 ns 10b = 12.5 ns 11b = 6.25 ns SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 849: Ucbxstatw Register
UCBBUSY Bus busy 0b = Bus inactive 1b = Bus busy Reserved Reserved SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 850: Ucbxtbcnt Register
UCASTPx is different from 00. Modify only when UCSWRST = 1. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 851: Ucbxrxbuf Register
Writing to the transmit data buffer clears the UCTXIFGx flags. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 852: Ucbxi2Coa0 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 853: Ucbxi2Coa1 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 854: Ucbxi2Coa3 Register
SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 855: Ucbxaddmask Register
MSB and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB. SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 856: Ucbxie Register
UCSTPIE STOP condition interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 857 UCRXIE0 Receive interrupt enable 0 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 858: Ucbxifg Register
(see the Byte Counter Interrupt section). 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 859 UCBxI2COA0 was on the bus in the same frame. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 860: Ucbxiv Register
1Ch = Interrupt Source: Clock low time-out; Interrupt Flag: UCCLTOIFG 1Eh = Interrupt Source: 9th bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest SLAU367P – October 2012 – Revised April 2020 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 861 This chapter describes the REF_A module..........................Topic Page ..................33.1 REF_A Introduction ..................33.2 Principle of Operation ....................33.3 REF_A Registers SLAU367P – October 2012 – Revised April 2020 REF_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 862: Ref_A Block Diagram
Request Reference (always with static mode) 1.2, 2.0, 2.5 V Switch REFVSEL REFGENREQ REFBGOT REFGENOT REFON BGMODE Figure 33-1. REF_A Block Diagram REF_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 863 The generation of the buffered bandgap voltage can be triggered by a timer or by software to make sure that the reference voltage is ready when a module requires it. SLAU367P – October 2012 – Revised April 2020 REF_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 864 LCD module in a mode that requires a reference voltage causes a REFBGREQ from the LCD module to be asserted. The buffered bandgap is made available on the bandgap reference line for use inside the LCD module. REF_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 865 Table 33-1. REF_A Registers Offset Acronym Register Name Type Access Reset Section REFCTL0 REFCTL0 Read/write Word 0000h Section 33.3.1 REFCTL0_L Read/write Byte REFCTL0_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 REF_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 866: Refctl0 Register
10b = 2.5 V available when reference requested or REFON = 1 11b = 2.5 V available when reference requested or REFON = 1 REF_A SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 867 Can be modified only when REFGENBUSY = 0. 0b = Disables reference if no other reference requests are pending 1b = Enables reference SLAU367P – October 2012 – Revised April 2020 REF_A Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 868 ADC12_B module..........................Topic Page ..................34.1 ADC12_B Introduction ..................34.2 ADC12_B Operation ..................34.3 ADC12_B Registers ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 869 Figure 34-1 shows the block diagram of ADC12_B. The reference generation is located in the reference module (REF) (see the device-specific data sheet). SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 870: Adc12_B Block Diagram
ADC12MEM31 ADC12MCTL31 Batt.Monitor Copyright © 2017, Texas Instruments Incorporated The MODCLK is part of the UCS. See the UCS chapter for more information. See the device-specific data sheet for timer sources available. See the device-specific data sheet for Internal Channel 0-3 availability and function. - Page 871 The user must ensure that the clock that is used for ADC12CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation does not complete and any result is invalid. SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 872: Analog Multiplexer T-Switch
REFOUT=1 or ADC12_B module reference when external reference with internal buffer is selected . So if REFOUT=1, VeREF+ buffered should not be selected with ADC12VRSEL = 0x3, 0x5, or 0xF. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 873 0011, 0101, 0111, 1001, 1011, 1101, or 1111. When SAMPCON is high, sampling is active. The high-to- low SAMPCON transition starts the conversion after synchronization with ADC12CLK plus one clock cycle (see Figure 34-3 Figure 34-4). SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 874: Extended Sample Mode Without Internal Reference In 12-Bit Mode
The ADC12SHTx bits select the sampling time in 4x multiples of ADC12CLK. ADC12SHT1x selects the sampling time for ADC12MEM8 to ADC12MEM23, and ADC12SHT0x selects the sampling time for ADC12MEM0 to ADC12MEM7 and ADC12MEM24 to ADC12MEM31. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 875: Pulse Sample Mode First Conversion Or Where Adc12Msc = 0 In 12-Bit Mode
R = Internal MUX-on input resistance C = Input capacitance = Parasitic capacitance, external Pext V = Capacitance-charging voltage pext Figure 34-7. Analog Input Equivalent Circuit SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 876: Adc12_B Conversion Result Formats
+V (0 to 4095) -128 to 127 8000h to 7F00h -512 to 511 8000h to 7FC0h -2048 to 2047 8000h to 7FF0h ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 877: Conversion Mode Summary
A sequence of channels is converted once. Repeat-single-channel A single channel is converted repeatedly. Repeat-sequence-of-channels (repeated autoscan) A sequence of channels is converted repeatedly. SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 878: Single-Channel Single-Conversion Mode, Adc12Issh
Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Conversion result is unpredictable. Figure 34-8. Single-Channel Single-Conversion Mode, ADC12ISSH = 0 ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 879: Sequence-Of-Channels Mode, Adc12Issh
ADC12EOS.x = 0 Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 34-9. Sequence-of-Channels Mode, ADC12ISSH = 0 SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 880: Repeat-Single-Channel Mode, Adc12Issh
ADC12ENC = 1 Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 34-10. Repeat-Single-Channel Mode, ADC12ISSH = 0 ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 881: Repeat-Sequence-Of-Channels Mode, Adc12Issh
ADC12EOS.x = 0) Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 34-11. Repeat-Sequence-of-Channels Mode, ADC12ISSH = 0 SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 882 The ADC12IN interrupt flag (ADC12INIFG) is set if the current result of the ADC12_B conversion is greater than the low threshold defined in register ADC12LO and less than the high threshold defined in ADC12HI. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 883: Typical Temperature Sensor Transfer Function
The reference choices for converting the temperature sensor are the same as with any other channel. –40 –20 Ambient Temperature (°C) Figure 34-12. Typical Temperature Sensor Transfer Function SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 884: Adc12_B Grounding And Noise Considerations
470 nF 10 F µ VEREF- Using an External Negative Reference 10 F µ 470 nF Figure 34-13. ADC12_B Grounding and Noise Considerations ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 885 ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC12IFG3 generates another interrupt. SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 886 ADIN ; Handle window comparator in window Interrupt RETI ; Return; ADRDY ; Handle window comparator in window Interrupt RETI ; Return; ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 887: 34.3 Adc12_B Registers
ADC12IER1_L Read/write Byte ADC12IER1_H Read/write Byte ADC12IER2 ADC12_B Interrupt Enable 2 Read/write Word 0000h Section 34.3.11 ADC12IER2_L Read/write Byte ADC12IER2_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 888 ADC12MCTL12_L Read/write Byte ADC12MCTL12_H Read/write Byte ADC12MCTL13 ADC12_B Memory Control 13 Read/write Word 0000h Section 34.3.6 ADC12MCTL13_L Read/write Byte ADC12MCTL13_H Read/write Byte ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 889 ADC12MCTL27_L Read/write Byte ADC12MCTL27_H Read/write Byte ADC12MCTL28 ADC12_B Memory Control 28 Read/write Word 0000h Section 34.3.6 ADC12MCTL28_L Read/write Byte ADC12MCTL28_H Read/write Byte SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 890 ADC12MEM10_H Read/write Byte undefined ADC12MEM11 ADC12_B Memory 11 Read/write Word undefined Section 34.3.5 ADC12MEM11_L Read/write Byte undefined ADC12MEM11_H Read/write Byte undefined ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 891 ADC12MEM25_H Read/write Byte undefined ADC12MEM26 ADC12_B Memory 26 Read/write Word undefined Section 34.3.5 ADC12MEM26_L Read/write Byte undefined ADC12MEM26_H Read/write Byte undefined SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 892 ADC12MEM30_H Read/write Byte undefined ADC12MEM31 ADC12_B Memory 31 Read/write Word undefined Section 34.3.5 ADC12MEM31_L Read/write Byte undefined ADC12MEM31_H Read/write Byte undefined ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 893: Adc12Ctl0 Register
1001b = 384 ADC12CLK cycles 1010b = 512 ADC12CLK cycles 1011b = Reserved 1100b = Reserved 1101b = Reserved 1110b = Reserved 1111b = Reserved SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 894: Adc12Ctl0 Register Description
ADC12SC and ADC12ENC may be set together with one instruction. ADC12SC is reset automatically. 0b = No sample-and-conversion-start 1b = Start sample-and-conversion ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 895: Adc12Ctl1 Register
110b = /7 111b = /8 ADC12SSELx ADC12_B clock source select 00b = ADC12OSC (MODOSC) 01b = ACLK 10b = MCLK 11b = SMCLK SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 896: Adc12Ctl1 Register Description
ADC12_B busy. This bit indicates an active sample or conversion operation. 0b = No operation is active. 1b = A sequence, sample, or conversion is active. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 897: Adc12Ctl2 Register
1b = Low power mode enable, ADC12CLK can not be greater than 1/4 the device-specific data sheet specified maximum for ADC12PWRMD = 0 SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 898: Adc12Ctl3 Register
The value of CSTARTADDx is 0h to 1Fh, corresponding to ADC12MEM0 to ADC12MEM31. Can be modified only when ADC12ENC = 0. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 899: Adc12Memx Register
2s-complement format during read back. If the user writes to the conversion memory registers, the results are corrupted. SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 900: Adc12Mctlx Register
ADC12ENC = 0. 0b = Not end of sequence 1b = End of sequence Reserved Reserved. Always reads as 0. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 901: Adc12Mctlx Register Description
11110b = If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 11111b = If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 902: Adc12Hi Register
2s-complement format. Bit 15 is the MSB. Bits 3-0 are 0 in 12-bit mode, bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8-bit mode. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 903: Adc12Ier0 Register
1b = Interrupt enabled ADC12IE3 Interrupt enable. Enables or disables the interrupt request for ADC12IFG3 bit. 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 904 1b = Interrupt enabled ADC12IE0 Interrupt enable. Enables or disables the interrupt request for ADC12IFG0 bit. 0b = Interrupt disabled 1b = Interrupt enabled ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 905: Adc12Ier1 Register
1b = Interrupt enabled ADC12IE19 Interrupt enable. Enables or disables the interrupt request for ADC12IFG19 bit. 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 906 1b = Interrupt enabled ADC12IE16 Interrupt enable. Enables or disables the interrupt request for ADC12IFG16 bit. 0b = Interrupt disabled 1b = Interrupt enabled ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 907: Adc12Ier2 Register
ADC12LO threshold and below the ADC12HI threshold. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled Reserved Reserved. Always reads as 0. SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 908: Adc12Ifgr0 Register
The ADC12IFG8 bit is reset if ADC12MEM8 is accessed, or it can be reset with software. 0b = No interrupt pending 1b = Interrupt pending ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 909: Adc12Ifgr0 Register Description
The ADC12IFG0 bit is reset if ADC12MEM0 is accessed, or it can be reset with software. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 910: Adc12Ifgr1 Register
The ADC12IFG24 bit is reset if ADC12MEM24 is accessed, or it can be reset with software. 0b = No interrupt pending 1b = Interrupt pending ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 911: Adc12Ifgr1 Register Description
The ADC12IFG16 bit is reset if ADC12MEM16 is accessed, or it can be reset with software. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 912: Adc12Ifgr2 Register
ADC12LO threshold and below the ADC12HI threshold interrupt. 0b = No interrupt pending 1b = Interrupt pending Reserved Reserved. Always reads as 0. ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 913: Adc12Iv Register
02Ch = Interrupt Source: ADC12MEM16 interrupt flag, Interrupt Flag: ADC12IFG16 02Eh = Interrupt Source: ADC12MEM17 interrupt flag, Interrupt Flag: ADC12IFG17 030h = Interrupt Source: ADC12MEM18 interrupt flag, Interrupt Flag: ADC12IFG18 SLAU367P – October 2012 – Revised April 2020 ADC12_B Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 914 048h = Interrupt Source: ADC12MEM30 interrupt flag, Interrupt Flag: ADC12IFG30 04Ah = Interrupt Source: ADC12MEM31 interrupt flag, Interrupt Flag: ADC12IFG31 04Ch = Interrupt Source: ADC12RDYIFG interrupt flag, Interrupt Flag: ADC12RDYIFG ADC12_B SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 915 16 channels..........................Topic Page ..................35.1 COMP_E Introduction ................... 35.2 COMP_E Operation ................... 35.3 COMP_E Registers SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 916: Comparator_E Block Diagram
CERSEL CEREF1 CEREF0 CERS CEOUTPOL 0001 Reference Voltage from shared Generator reference 1110 1111 Figure 35-1. Comparator_E Block Diagram Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 917 The CESHORT bit shorts the Comparator_E inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 35-2. SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 918: Comparator_E Sample-And-Hold
Enable the output filter to reduce errors associated with comparator oscillation. Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 919: Rc-Filter Response At The Output Of The Comparator
TI recommends setting CEREFLx = 00 before changing the CEREFLx settings. SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 920: Transfer Characteristic And Power Dissipation In A Cmos Inverter And Buffer
Figure 35- 6. A reference resistor Rref is compared to Rmeas. Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 921: Temperature Measurement System
SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 922 × C × ln meas meas ref1 –R × C × ln meas meas meas = R × meas Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 923 CEINT Comparator_E interrupt register Read/write Word 0000h Section 35.3.5 CEIV Comparator_E interrupt vector word Read Word 0000h Section 35.3.6 SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 924: Cectl0 Register
Reserved. Reads as 0. CEIPSEL Channel input selected for the V+ terminal of the comparator if CEIPEN is set to Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 925: Cectl1 Register
Output value. This bit reflects the value of the Comparator_E output. Writing this bit has no effect on the comparator output. SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 926: Cectl2 Register
VREF is applied to the V+ terminal CEREF0 Reference resistor tap 0. This register defines the tap of the resistor string while CEOUT = 0. Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 927: Cectl3 Register
Comparator_E. The bit CEPD7 disables the port of the comparator channel 7. 0b = The input buffer is enabled. 1b = The input buffer is disabled. SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 928 Comparator_E. The bit CEPD0 disables the port of the comparator channel 0. 0b = The input buffer is enabled. 1b = The input buffer is disabled. Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 929: Ceint Register
Comparator_E output interrupt flag. The bit CEIES defines the transition of the output setting this bit. 0b = No interrupt pending. 1b = Output interrupt pending. SLAU367P – October 2012 – Revised April 2020 Comparator E (COMP_E) Module Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 930: Ceiv Register
06h = Reserved 08h = Reserved 0Ah = Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest Comparator E (COMP_E) Module SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 931 The differences between LCD_B and LCD_C are listed in Table 36-1..........................Topic Page ..................36.1 LCD_C Introduction ....................36.2 LCD_C Operation ....................36.3 LCD_C Registers SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 932: Differences Between Lcd_B And Lcd_C
The maximum number of segment lines and memory registers available differs with device. See the device-specific data sheet for available segment pins and the maximum number of segments supported. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 933: Lcd Controller Block Diagram
VLCDREFx VLCDx Regulated Charge Pump/ LCD Bias Generator Contrast Control LCDCPEN LCDCAP/R33 LCDREF/R13 LCD2B EXTBIAS Figure 36-1. LCD Controller Block Diagram SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 934: Lcd Memory For Static And 2-Mux To 4-Mux Mode - Example For 160 Segments
LCDM2 1, 0 LCDM1 Sn+1 Figure 36-2. LCD Memory for Static and 2-Mux to 4-Mux Mode - Example for 160 Segments LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 935: Lcd Memory For 5-Mux To 8-Mux Mode - Example For 160 Segments
= 32768 Hz, LCDPREx = 011, and LCDDIVx = 10101: ACLK/VLOCLK = 32768 Hz / ((21+1) × 2 ) = 32768 Hz / 176 = 186 Hz SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 936 With LCDDISP = 0, the LCD memory is selected, and with LCDDISP = 1 the blinking memory is selected as display memory. Switching between the memories is synchronized to the frame boundaries. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 937 VLCDx bits setting. When VLCDEXT = 1, V is sourced externally from the LCDCAP, pin and the internal charge pump is disabled. SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 938: Bias Generation
Figure 36-4. Bias Generation The internally generated bias voltages V2 to V4 are switched to external pins with LCDREXT = 1. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 939: Bias Voltages And External Pins
LCDREXT = 1 or LCDEXTBIAS = 1 5-mux to 8-mux V4 ("1/3") if LCDREXT = 1 or LCDEXTBIAS = 1 V5 ("0") if R03EXT = 1 SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 940: Lcd Voltage And Biasing Characteristics
LCDSx bits as for all other segment pins. See the port schematic section of the device-specific data sheet for details on controlling the pin functionality. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 941 The LCDFRMIFG is set at a frame boundary. It is automatically cleared when a LCD or blinking memory register is written. Setting the LCDFRMIFGIE bit enables the interrupt. SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 942 RETI ; Back to main program LCDBLKOFF_HND ; Vector 6: LCDBLKOFFIFG ... ; Task starts here RETI ; Back to main program LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 943: Example Static Waveforms
COM0 COM0 frame COM0-S0 Segment is on. −V1 COM0-S1 Segment is off. −V1 Figure 36-5. Example Static Waveforms SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 944: Example 2-Mux Waveforms
2-mux 1/2-bias waveforms. COM0 COM0 frame COM1 COM1 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-6. Example 2-Mux Waveforms LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 945: Example 3-Mux Waveforms
COM0 COM0 frame COM1 COM1 COM2 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-7. Example 3-Mux Waveforms SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 946: Example 4-Mux Waveforms
COM0 frame COM1 COM1 COM2 COM3 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-8. Example 4-Mux Waveforms LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 947: Example 6-Mux Waveforms
COM1 COM1 COM2 COM3 COM4 COM5 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-9. Example 6-Mux Waveforms SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 948: Example 8-Mux, 1/3 Bias Waveforms (Lcdlp = 0)
COM7 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-10. Example 8-Mux, 1/3 Bias Waveforms (LCDLP = 0) LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 949: Example 8-Mux, 1/3 Bias Low-Power Waveforms (Lcdlp = 1)
COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 36-11. Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1) SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 950: Lcd_C Control Registers
Section 36.3.10 014h Reserved 016h Reserved 018h Reserved 01Ah Reserved 01Ch Reserved 01Eh LCDCIV LCD_C interrupt vector Read/write 0000h Section 36.3.11 LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 951: Lcd_C Memory Registers For Static And 2-Mux To 4-Mux Modes
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 952: Lcd Blinking Memory Registers For Static And 2-Mux To 4-Mux Modes
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 953: Lcd Memory Registers For 5-Mux To 8-Mux
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 954 Reserved 056h Reserved 057h Reserved 058h Reserved 059h Reserved 05Ah Reserved 05Bh Reserved 05Ch Reserved 05Dh Reserved 05Eh Reserved 05Fh Reserved LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 955: Lcdcctl0 Register
0b = Standard LCD waveforms on segment and common lines selected 1b = Low-power LCD waveforms on segment and common lines selected SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 956 LCD on. This bit turns the LCD_C module on or off. 0b = LCD_C module off 1b = LCD_C module on LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 957: Lcdcctl1 Register
LCD frame interrupt flag. Automatically cleared when data is written into a memory register. 0b = No interrupt pending 1b = Interrupt pending SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 958: Lcdcblkctl Register
11b = Switching between display contents as stored in LCDMx and LCDBMx memory registers. In mux mode >5 blinking is disabled. LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 959: Lcdcmemctl Register
When returning to LCDBLKMODx = 00 the bit is cleared. 0b = Display content of LCD memory registers LCDMx 1b = Display content of LCD blinking memory registers LCDBMx SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 960: Lcdcvctl Register
NOTE: Should be changed only while LCDON = 0. 0b = V is generated internally 1b = V is sourced externally LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 961 Bias select. LCD2B is ignored in static mode or mux modes ≥5. NOTE: Should be changed only while LCDON = 0. 0b = 1/3 bias 1b = 1/2 bias SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 962: Lcdcpctl0 Register
NOTE: Settings for LCDSx should be changed only while LCDON = 0. 0b = Multiplexed pins are port functions 1b = Pins are LCD functions LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 963: Lcdcpctl2 Register
NOTE: Settings for LCDSx should be changed only while LCDON = 0. 0b = Multiplexed pins are port functions 1b = Pins are LCD functions SLAU367P – October 2012 – Revised April 2020 LCD_C Controller Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 964: Lcdccpctl Register
06h = Interrupt Source: Blink, segments on; Interrupt Flag: LCDBLKONIFG 08h = Interrupt Source: Frame interrupt; Interrupt Flag: LCDFRMIFG; Interrupt Priority: Lowest LCD_C Controller SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 965 This document describes the Extended Scan interface..........................Topic Page ....................37.1 ESI Introduction ....................37.2 ESI Operation ....................37.3 ESI Registers SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 966: Esi Block Diagram
Timing State Machine (TSM) ESIDVSS from 32kHz ½ with RAM crystal osc. ESIDVCC with oscillator AVcc SMCLK Figure 37-1. ESI Block Diagram Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 967 Throughout this chapter, signals from the ESITSMx registers (x = 0 to 31) are noted in the signal name with (tsm). For example, the signal ESIEX(tsm) comes from the actual active ESITSMx register. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 968: Esi Analog Front End Afe1 Block Diagram
AFE2 is disabled (ESICA2EN = 0 and ESIDAC2EN = 0), the AFE2 comparator output is always low (0 level). Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 969: Esi Analog Front End Afe2 Block Diagram
At the end of the measurement, the sensor should be damped by setting ESILCEN(tsm) = 0 to remove any residual energy before the next measurement. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 970: Excitation And Sample-And-Hold Circuitry
The sample-and-hold is used for resistive dividers or for other analog signals that should be sampled. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 971: Analog Input Equivalent Circuit
ESIOUTx output bits and the ESITCHOUTx output bits for the comparator output as described in Table 37-2. TESTDX is controlled by the ESITESTD bit. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 972: Analog Front-End Output Timing
ESICA2INV for AFE2. The comparator output is stored in the selected output bit and processed by the processing state machine to detect motion and direction. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 973: Analog Hysteresis With Dac Registers
When TESTDX = 1, the ESIDAC1R6 and ESIDAC1R7 registers are used as the comparator reference as described in Table 37-4. Note that this feature is only available in AFE1. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 974: Dac Register Select When Testdx=1
TSM sequence is completed and the system is again in idle mode (ESITSM0 settings are used in idle mode). Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 975: Timing State Machine Block Diagram
TSM sequence is in progress ESIOSC ESICLKGON SMCLK Enable request ESICNT3 ESIHFSEL Figure 37-8. Timing State Machine Block Diagram SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 976 Table 37-5. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 977: Tsm State Duration
TESTDX is generated after the ESITESTD bit is set and the next TSM sequence completes. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 978: Test Cycle Insertion
Table 37-6. TSM Example Register Values TSMx Register TSMx Register Contents ESITSM5 0100Ah ESITSM6 00402h ESITSM7 01912h ESITSM8 00952h ESITSM9 00200h Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 979: Timing State Machine Example
The ESICHx(tsm), ESITCH0x, or ESITCH1x bits define which of the latches is used. The block diagram of the Pre-Processing Unit is shown in Figure 37-11. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 980: Pre-Processing Unit
Timer_A capture/compare registers. This can be used to measure the time between excitation of a sensor and the last oscillation that passes through the comparator or to perform a slope A/D conversion. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 981: Esi Processing State Machine Block Diagram
(Q0...Q7) from the PSM state table located in ESI RAM to the PSM next state latch (V2...V6 or V3...V6). All accesses to the PSM state table are done automatically with no CPU intervention. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 982 ESIOSC cycle. The worst-case time between state transitions in this case is 6 ESIOSC cycles. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
- Page 983 TSM sequences. Alternatively, the ESI counters may be read multiple times, and a majority vote taken in software to determine the correct reading. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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Page 984: Simplest Psm State Diagram (Esiv2Sel=1)
The state table entry for state 11 is loaded at the next state transition: V6 (Q6) V5 (Q5) V4 (Q4) V3 (Q3) V2 (Q0) V1 (PPUS2) V0 (PPUS1) Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 985: 37.2.7 Esi Interrupts
ESIIFG3 is set as soon as the content of ESICNT1 counter is equal to the content of ESITHR1 or ESITHR2. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 986: Lc Sensor Oscillations
ESIDVCC Undamped Oscillation Undamped Envelopes AV /2 Damped Envelopes Damped Oscillation Time Figure 37-15. LC Sensor Oscillations Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 987: Sensor Connections For The Oscillation Test
ESICH1 ESICH0 0..1k ESICOM 470 nF ESIDVSS Power Supply Terminals /ESIDVCC Figure 37-16. Sensor Connections For The Oscillation Test SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 988: Lc Sensor Connections For The Envelope Test
ESICH0 0..1k ESICOM 470 nF ESIDVSS Power Supply Terminals /ESIDVCC Figure 37-17. LC Sensor Connections For The Envelope Test Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 989: Lc Sensor Connections For The Envelope Test
ESICH0 0..1k ESICOM 470 nF ESIDVSS Power Supply Terminals /ESIDVCC Figure 37-18. LC Sensor Connections For the Envelope Test SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 990: Resistive Sensor Connections
ESICI3 ESICI2 ESICI1 ESICI0 ESICH3 ESICH2 ESICH1 ESICH0 ESICOM ESIDVSS Power Supply Terminals /ESIDVCC Figure 37-19. Resistive Sensor Connections Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 991: Sensor Position And Quadrature Signals (S1=Ppus1, S2=Ppus2)
Table 37-8. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 992: Quadrature Decoding Psm Table
Error 041h No rotation 008h Turns left 009h Error 040h Turns left 001h Turns right 008h No rotation 009h Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 993: 37.3 Esi Registers
Word Unchanged ESIDAC2R7 60h to 9Eh ESITSM0 to ESI TSM 0 to ESI TSM 31 Read/Write Word Unchanged ESITSM31 SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 994: Esidebug1 Register
Table 37-12. ESIDEBUG3 Register Description Field Type Reset Description 15-0 Register_Content Current ESITSMx register content. These bits show the TSM output. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 995: Esidebug4 Register
These bits show which DAC2 register is currently selected to control the DAC2. 11-0 DAC2_Data These bits show value of the currently selected DAC2 register. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 996: Esicnt0 Register
ESICNT1. These bits are the ESICNT1 counter. ESICNT1 is reset when ESIEN = 0 or when ESICNT1RST = 1. Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 997: Esicnt2 Register
ACLK period after ESICLKGON and ESIHFSEL are both set. Setting the control bits ESIHFSEL and ESICLKGON resets the ESICNT3 counter. SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 998: Esiiv Register
Interrupt Flag: ESIIFG7 12h = Interrupt Source: Start of a TSM sequence; Interrupt Flag: ESIIFG2; Interrupt Priority: Lowest Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... -
Page 999: Esiint1 Register
ESIIFG5 bit. Details about the interrupt functionality can be found in the ESIIFG5 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled SLAU367P – October 2012 – Revised April 2020 Extended Scan Interface (ESI) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated... - Page 1000 ESIIFG0 bit. Details about the interrupt functionality can be found in the ESIIFG0 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled 1000 Extended Scan Interface (ESI) SLAU367P – October 2012 – Revised April 2020 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated...
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