Related Manuals for XESS XSV
Summary of Contents for XESS XSV
- Page 1 2608 Sweetgum Drive Apex NC 27502 Toll-free: 800-549-9377 International: 919-387-0076 FAX: 919-387-1302 XSV Board V0.1 Manual XSV Board V0.1 Manual How to install and use your new XSV Board RELEASE DATE: 9/11/1999...
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Page 2: Limited Warranty
(1) year and will conform to XESS’s specification therefor. This limited warranty shall commence on the date appearing on your purchase receipt. XESS shall have no liability for any Product returned if XESS determines that the asserted defect a) is not present, b) cannot reasonably be rectified because of damage occurring before XESS receives the Product, or c) is attributable to misuse, improper installation, alteration, accident or mishandling while in your possession. -
Page 3: Table Of Contents
Table of Contents Limited Warranty ..................1 Preliminaries ....................4 Getting Help! ....................4 Packing List ....................4 XSV Overview....................5 XSV Board Features ................5 Installation .......................8 Unpacking the Board................8 Configuring the Jumpers ................8 Applying Power ..................8 Connecting to a PC ..................8 Setting the Oscillator Frequency...............8 Programming the Interface..............10... - Page 4 Digit and Bargraph LEDs................24 PS/2 Port....................26 Dual USB Port..................26 Parallel Port....................27 Serial Port....................29 Xchecker Cable..................29 Power Connectors..................30 XSV Pin Connections..................31 XSV Schematics ...................33...
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Page 5: Preliminaries
Packing List Here is what you should have received in your package: an XSV Board; a 6-foot, 25-wire cable with a male DB25 connector at each end; a 3.5" floppy diskette or CDROM with documentation on the XSV Board. -
Page 6: Xsv Overview
The XSV Board accepts Virtex FPGAs from 50K to 800K gates in size. The XSV can digitize PAL, SECAM, or NTSC video with up to 9-bits of resolution on the red, green, and blue channels and can output video images through a 110 MHz, 24-bit RAMDAC. - Page 7 Xchecker cable interface allows downloading and readback of the FPGA configuration. ATX power connector or 9 VDC power jack lets the XSV Board receive power from a standard ATX power supply or a 9 VDC power supply. The location of these resources are indicated in the simplified view of the XSV Board...
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Page 9: Installation
CPLD. The oscillator has an internal 100 MHZ frequency source that is scaled by a divisor between 1 and 2048 to generate the clock signal for the rest of the XSV Board. The divisor is stored in non-volatile memory in the oscillator chip so it will be restored each time power is applied to the XSV Board. - Page 10 Remove power and the parallel port cable from the XSV Board. Remove the shunt on jumper J24. Restore power and the parallel port cable to the XSV Board. The clock frequency should now be 100 MHz ÷ DIVISOR. You can substitute an external clock source for the internal oscillator. Follow these steps to configure the programmable oscillator for operation with an external clock source: Remove power from the XSV Board.
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Page 11: Programming The Interface
Place a shunt on jumper J23. Restore power to the XSV Board. Reconnect the cable to the PC parallel port. Enter the following command in a DOS window if you want to program the XSV Board through the PC parallel port: XSINTFC PARALLEL (The serial and Flash memory interfaces are not currently implemented.) -
Page 12: Xsv Circuitry
FPGA. The divisor is stored in EEPROM in the DS1075 so it will be restored whenever power is applied to the XSV Board. To get a precise frequency value or to sync the XSV circuitry with an external system, you can insert an external clock signal through connector J27. This external clock replaces the 100 MHz internal oscillator of the DS1075. -
Page 13: Mbit Flash Ram
FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the Flash bitstream whenever the XSV Board is powered up. After power-up, the FPGA can read and/or write the Flash. (Of course, the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash.) The... - Page 14 Flash RAM Virtex XC95108 FPGA Pin CPLD Pin /RESET...
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Page 15: Sram Banks
SRAM Banks The FPGA has access to two independent banks of SRAM as shown below: Each SRAM bank is organized as 512K × 16 bits. The FPGA pins connected to the SRAM banks are shown in the accompanying table. 0 - 7 0 - 7 4 Mbit 4 Mbit... -
Page 16: Video Decoder
Bank Video Decoder The XSV Board can digitize NTSC, SECAM, and PAL video signals using the SAA7113 video decoder. The digitized video arrives at the FPGA over the VPO bus. The arrival of video data is synchronized with the rising edge of the LLC (line-locked clock) from the video decoder. -
Page 17: Ramdac And Vga Monitor Interface
SAA7113 Virtex FPGA Pin VPO0 VPO1 VPO2 VPO3 VPO4 VPO5 VPO6 VPO7 RAMDAC and VGA Monitor Interface The FPGA can generate a video signal for display on a VGA monitor either directly or using a RAMDAC depending upon the arrangement of the shunts on jumpers J5, J6, and vsync hsync Connector... - Page 18 with the PIXELCLK generated by the FPGA. The FPGA lowers the /BLANK signal when the pixels fall outside the desired visible area of the monitor screen. The colormap of the RAMDAC is initialized by the FPGA using the D bus along with the RS, /WR, and /RD signals.
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Page 19: Stereo Codec
SDOUT Ethernet PHY The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps. The Ethernet PHY chip connects to both the FPGA and the CPLD. The FPGA acts as a MAC (media access controller) and manages the transfer of data packets to and from the PHY chip, while the CPLD controls the configuration pins that determine the operational mode of the PHY chip. - Page 20 (/LEDS), the receiver is active (/LEDR), the transmitter is active (/LEDT), the link is active (/LEDL), and a collision is detected (/LEDC). The CPLD can relay these signals to the LEDs on the XSV Board if you wish to display the Ethernet status.
- Page 21 The connections of the PHY chip to the FPGA and CPLD are listed below. Note that the FPGA shares some connections between the PHY chip and the RAMDAC. The RAMDAC pins are used to load the colormap and should not be active except during system initialization.
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Page 22: Expansion Headers
Expansion Headers The XSV Board has two 50-pin headers (J25 and J26) which connect the FPGA to external systems. The arrangement of the headers is shown below: Virtex FPGA The connections between the FPGA and the expansion headers are listed below. The FPGA pins which connect to the left and right expansion headers are also connected to the left and right banks of SRAM, respectively. - Page 23 Expansion Virtex Virtex SRAM Connector FPGA Pin FPGA Pin Function to Left to Right Connector Connector +3.3 +3.3 +3.3...
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Page 24: Pushbuttons And Eight-Position Dip Switch
Pushbuttons and Eight-Position DIP Switch The XSV Board has a bank of eight DIP switches and four pushbuttons that are accessible from the FPGA. The CPLD is also connected to the DIP switches and one of the pushbuttons. When pressed, each pushbutton pulls the connected pin of the FPGA and CPLD to ground. -
Page 25: Digit And Bargraph Leds
DIPSW8 Digit and Bargraph LEDs The XSV Board has a 10-segment bargraph LED and two more 7-segment LED digits for use by the FPGA and CPLD. All of these LEDs are active-high meaning that an LED segment will glow when a logic-high is applied to it. - Page 26 S2 S3 S2 S3 XC95108 Virtex CPLD FPGA Virtex XC95108 Flash RAM FPGA Pin CPLD Pin Function...
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Page 27: Ps/2 Port
Virtex FPGA Pin DATA Dual USB Port The XSV Board has a dual-USB interface (J15) that can be connected to a variety of high- speed or low-speed USB peripherals. The FPGA receives two differential data signals from each USB port. -
Page 28: Parallel Port
The speed of the upper and lower USB ports is set by jumpers J19 and J18, respectively. If the USB peripheral connected to the upper or lower port needs to draw power from the XSV Board, then a shunt should be placed on jumper J17 or J16, respectively. Upper = 12 Mbps Upper = 1.5 Mbps... - Page 29 TMS signal steers the actions of the programming state machine. The TDO pin outputs information back through the parallel port. Removing the shunt from jumper J23 isolates the TCK pin from the parallel port so the CPLD will not be inadvertently reprogrammed during routine parallel port operations.
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Page 30: Serial Port
Serial Port The CPLD handles the interface to the serial port. The four active lines of the serial port connect to general-purpose I/O pins on the CPLD as follows. Serial Port XC95108 CPLD Pin Serial Port XC95108 Connector CPLD (J28) level shifters Xchecker Cable... -
Page 31: Power Connectors
J11. The connector is keyed so power cannot be applied with the wrong polarity. The XSV Board can also be powered from a 9 VDC power supply through jack J12. The power supply must have a 2.1mm, center-positive plug. Voltage regulators will generate... -
Page 32: Xsv Pin Connections
XSV Pin Connections The table below lists the pin numbers of the XC95108 CPLD and the pin names of the other chips that they connect to. 1 /LEDS 26 +5V 51 +5V 76 LP15 2 CFG1 27 Af8-B2 52 Af14-DIPSW2... - Page 33 1 GND 61 +3.3V 121 +3.3V 181 TDO 2 TMS 62 M2 122 /PROGRAM 182 GND 3 MCLK 63 Ar4 123 /init* 183 TDI 4 LRCK 64 Ar3 124 Df7-Sr0 184 /cs* 5 SCLK 65 Ar2 125 VPO3 185 /write*-SW4 6 SDIN 66 Ar1 126 VPO4...
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Page 34: Xsv Schematics
XSV Schematics The following pages show the detailed schematics for the XSV Board. - Page 50 XSV Board V0.1 Layout...