Video Decoder - XESS XSV Manual

Video Decoder

The XSV Board can digitize NTSC, SECAM, and PAL video signals using the SAA7113
video decoder. The digitized video arrives at the FPGA over the VPO bus. The arrival of
video data is synchronized with the rising edge of the LLC (line-locked clock) from the
video decoder. The FPGA programs the video options of the SAA7113 using the I
(SCL and SDA).
Virtex
FPGA
SRAM Pin Virtex
FPGA Pin
to Left
Bank
A1 199
A2 195
A3 194
A4 193
A5 192
A6 191
A7 189
A8 188
A9 187
A10 238
A11 237
A12 236
A13 235
A14 234
A15 232
A16 231
A17 230
A18 229
8
vpo
0 - 7
rts0
SAA7113
rts1
Video
rtco
llc
Decoder
scl
sda
SAA7113 Virtex
Pin FPGA Pin
LLC 92
RTS0 111
RTS1 110
RTCO 113
15
Virtex
FPGA Pin
to Right
Bank
66
65
64
63
57
56
55
54
53
108
107
103
102
101
100
99
97
96
S-Video
luma
ai11
Connector
ai12
chroma
ai21
RCA Jack
ai22
cvbs
2
C bus
(J8)
(J9)