Stereo Codec; Ethernet Phy - XESS XSV Manual

Stereo Codec

The XSV Board has a stereo codec that accepts two analog input channels from jack J1,
digitizes the analog values, and sends the digital values to the FPGA as a serial bit
stream. The codec also accepts a serial bit stream from the XS Board and converts it into
two analog output signals, which exit the XSV Board through jack J2. The serial bit
streams are synchronized with a clock from the FPGA that enters the codec on SCLK
signal. The FPGA uses the LRCK signal to select the left or right channel as the
source/destination of the serial data. The master clock from the FPGA (MCLK)
synchronizes all the internal operations of the codec.
Virtex
FPGA
The FPGA pins which connect to the codec are as follows:

Ethernet PHY

The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps. The Ethernet PHY chip
connects to both the FPGA and the CPLD. The FPGA acts as a MAC (media access
controller) and manages the transfer of data packets to and from the PHY chip, while the
CPLD controls the configuration pins that determine the operational mode of the PHY
chip.
Direct RAMDAC
VGA Pin Pin
D2
D3
D4
D5
D6
D7
mclk
lrck
AK4520A
sclk
Codec
sdin
sdout
Stereo
Codec Pin
MCLK
LRCK
SCLK
SDIN
SDOUT
Virtex LXT970A
FPGA Pin Function
40 TXD2
39 TXD3
38 RXD0
36 RXD1
35 RXD2
34 RXD3
in
l e f t
in
r i g h t
out
l e f t Amp
out
r i g h t
Virtex
FPGA Pin
3
4
5
6
7
18
Stereo Jack
(J1)
Stereo Jack
(J2)