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XESS XSV Manual

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2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
International: 919-387-0076
FAX: 919-387-1302
XSV Board V1.1 Manual
XSV Board V1.1 Manual
XSV Board V1.1 Manual
XSV Board V1.1 Manual
How to install and use
your new XSV Board
XSV BOARD V1.1 MANUAL
RELEASE DATE: 9/21/2001

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  • Page 1 2608 Sweetgum Drive Apex NC 27502 Toll-free: 800-549-9377 International: 919-387-0076 FAX: 919-387-1302 XSV Board V1.1 Manual XSV Board V1.1 Manual XSV Board V1.1 Manual XSV Board V1.1 Manual How to install and use your new XSV Board XSV BOARD V1.1 MANUAL...
  • Page 2 Copyright ©1999-2001 by X Engineering Software Systems Corporation. All XS-prefix product designations are trademarks of XESS Corp. All XC-prefix product designations are trademarks of Xilinx. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher.
  • Page 3 Unpacking the Board ...................8 Configuring the Jumpers................8 Applying Power ....................8 Connecting to a PC ..................9 Testing the XSV Board ................9 Setting the Oscillator Frequency ....Error! Bookmark not defined. Programming the Interface ................11 Downloading Virtex Configuration Bitstreams ..........13 Downloading Virtex Configuration Bitstreams to FlashError! Bookmark not defined.
  • Page 4 Ethernet PHY....................25 Expansion Headers..................28 Pushbuttons and Eight-Position DIP Switch..........30 Digit and Bargraph LEDs ................31 PS/2 Port.....................33 USB Port.....................33 Parallel Port ....................34 Serial Port ....................36 Xchecker Interface ..................37 Power Connectors..................38 XSV Pin Connections ..................39 XSV Schematics ....................40...
  • Page 5 Here is what you should have received in your package: an XSV Board; a 6-foot, 25-wire cable with a male DB25 connector at each end; an XSTOOLs CDROM with software utilities and documentation for using the XSV Board. XSV BOARD V1.1 MANUAL...
  • Page 6 The XSV Board has a single Virtex FPGA from 50K to 800K gates in size. The XSV can digitize PAL, SECAM, or NTSC video with up to 9-bits of resolution on the red, green, and blue channels and can output video images through a 110 MHz, 24-bit RAMDAC.
  • Page 7 Xchecker cable interface allows downloading and readback of the FPGA configuration. ATX power connector or 9 VDC power jack lets the XSV Board receive power from a standard ATX power supply or a 9 VDC power supply. The locations of these resources are indicated in the simplified view of the XSV Board shown below.
  • Page 8 16 Mbit Flash CPLD 512K x 8 512K x 8 SRAM SRAM Virtex FPGA (XCV50-800) 512K x 8 512K x 8 SRAM SRAM Pushbuttons Ether Stereo Stereo PS/2 RJ45 Input Output Port Port Port Output XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 9 You should place the XSV Board on a non-conducting surface. Configuring the Jumpers Your XSV Board should arrive with the shunts set on the jumpers in their default arrangement. The minimal shunt arrangement to allow testing of your XSV Board is as follows: 1.
  • Page 10 GXSTEST will configure the FPGA to perform a test procedure on your XSV Board. After several seconds you will see a O O O O displayed on the LED digit if the test completes successfully. Otherwise an E E E E will be displayed if the test fails. A status window will also appear on your PC screen informing you of the success or failure of the test.
  • Page 11 XSTOOLS installation. This brings up the window shown below. Your next step is to select the parallel port that your XSV Board is connected to from the Port pulldown list. Then select your particular XSV Board from the Board Type pulldown list.
  • Page 12 XSTOOLS installation. This brings up the window shown below. Then select the type of XSV Board you are using and the parallel port to which it is connected as described previously.
  • Page 13 Clicking on the Load button will begin sending the .SVF file to the CPLD on the XSV Board through the parallel port connection. During the downloading process, GXSLOAD will display the name of the file and the progress of the current download.
  • Page 14 2 and 3 of jumper J31. Then drag & drop one or more .BIT files for the type of Virtex FPGA on your XSV Board into the FPGA/CPLD area of the GXSLOAD window. Clicking your mouse on a file name will highlight the name and select the file for downloading.
  • Page 15 Storing Non-Volatile Designs in Your XSV Board The Virtex FPGA on the XSV Board stores its configuration in an on-chip SRAM which is erased whenever power is removed. Once your design is finished, you may want to store the bitstream in the 2 MByte Flash device on the XSV Board which configures the FPGA for operation as soon as power is applied.
  • Page 16 Then click on the file icon and drag & drop it into any folder. This activates the following sequence of steps: 1. The CPLD on the XSV Board is reprogrammed to create an interface between the Flash device and the PC parallel port.
  • Page 17 After the data is uploaded from the Flash, the CPLD on the XSV Board is left with the Flash interface programmed into it. You will need to reprogram the CPLD with either the parallel port or Flash configuration circuit before the board will function again. The CPLD configuration bitstreams are stored in the following files: XSTOOLS\XSV\dwnldpar.svf: Drag &...
  • Page 18 2N and the lower eight bits at location 2N+1. This byte-ordering applies for both RAM uploads and downloads. The XSV RAM is organized into a 512K x 16 right bank (RAM chips U33 and U34) and a 512K x 16 left bank (RAM chips U35 and U36). With respect to the GXSLOAD upload/download process, the right bank is located in the byte address range [0x000000–...
  • Page 19 2 and 3 to make the oscillator output a clock signal upon power-up. To get a precise frequency value or to sync the XSV circuitry with an external system, you can insert an external clock signal through pin 1 of connector J27 and place a shunt across pins 2 and 3 of jumper J36.
  • Page 20 FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the Flash bitstream whenever the XSV Board is powered up. After power-up, the FPGA can read and/or write the Flash. (Of course, the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash.) The...
  • Page 21 Flash RAM Virtex XC95108 FPGA Pin CPLD Pin /RESET XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 22 FPGA 0 - 1 8 0 - 1 8 4 Mbit 4 Mbit SRAM SRAM 0 - 7 0 - 7 SRAM Pin Virtex Virtex FPGA Pin FPGA Pin to Left to Right Bank Bank XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 23 Bank Bank Video Decoder The XSV Board can digitize NTSC, SECAM, and PAL video signals using the SAA7113 video decoder (http://www-us.semiconductors.philips.com/pip/SAA7113H). The digitized video arrives at the FPGA over the VPO bus. The arrival of video data is synchronized with the rising edge of the LLC (line-locked clock) from the video decoder. The FPGA programs the video options of the SAA7113 using the I C bus (SCL and SDA).
  • Page 24 P bus to pass the index of the color for the current pixel. The index is used to lookup the 24-bit color value (eight bits for the red, green, and blue components) stored in the XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 25 Ethernet data transmission and reception and are usually only active after system initialization. Direct RAMDAC Virtex LXT970A VGA Pin FPGA Pin Function PIXELCLK /HSYNC /HSYNC /VSYNC /VSYNC /BLANK RED0 RED1 GREEN0 GREEN1 BLUE0 BLUE1 TXD4 RX_ER RX_DV TXD0 XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 26 SCLK SDIN SDOUT Ethernet PHY The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps. The LXT970A Ethernet PHY chip (http://128.11.21.45/scripts/mardev/product/lxt970.asp ) connects to both the FPGA and the CPLD. The FPGA acts as a MAC (media access controller) and manages the transfer of data packets to and from the PHY chip, while the CPLD controls the configuration pins that determine the operational mode of the PHY chip.
  • Page 27 (/LEDS), the receiver is active (/LEDR), the transmitter is active (/LEDT), the link is active (/LEDL), and a collision is detected (/LEDC). The CPLD can relay these signals to the LEDs on the XSV Board if you wish to display the Ethernet status. XSV BOARD V1.1 MANUAL...
  • Page 28 Virtex XC95108 RAMDAC FPGA Pin CPLD Pin TRSTE TX_CLK TX_EN TX_ER TXD0 TXD1 TXD2 TXD3 TXD4 RX_CLK RX_DV RX_ER RXD0 RXD1 RXD2 RXD3 RXD4 FDS/MDINT MDIO MDDIS CFG0 CFG1 /RESET /LEDS /LEDR /LEDT /LEDL /LEDC XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 29 Expansion Headers The XSV Board has two 50-pin headers (J25 and J26) which connect the FPGA to external systems. The arrangement of the headers is shown below: Virtex FPGA The connections between the FPGA and the expansion headers are listed below. The FPGA pins which connect to the left and right expansion headers are also connected to the left and right banks of SRAM, respectively.
  • Page 30 Expansion Virtex Virtex SRAM Connector FPGA Pin FPGA Pin Function to Left to Right Connector Connector +3.3 +3.3 +3.3 XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 31 Pushbuttons and Eight-Position DIP Switch The XSV Board has a bank of eight DIP switches and four pushbuttons that are accessible from the FPGA. The CPLD is also connected to the DIP switches and one of the pushbuttons. When pressed, each pushbutton pulls the connected pin of the FPGA and CPLD to ground.
  • Page 32 DIPSW8 Digit and Bargraph LEDs The XSV Board has a 10-segment bargraph LED and two more 7-segment LED digits for use by the FPGA and CPLD. All of these LEDs are active-high meaning that an LED segment will glow when a logic-high is applied to it.
  • Page 33 S2 S3 S2 S3 XC95108 Virtex CPLD FPGA Virtex XC95108 Flash RAM FPGA Pin CPLD Pin Function XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 34 DATA USB Port The XSV Board has a USB interface (J35) that can be connected to a variety of high- speed or low-speed USB peripherals. The FPGA interfaces to the two differential data signals from the USB port through a PDIUSBP11A USB interface chip (http://www- us.semiconductors.philips.com/pip/PDIUSBP11A_2).
  • Page 35 J33 and J34. If the USB peripheral connected to the port needs to draw power from the XSV Board, then a shunt should be placed on jumper J16. The connections of the FPGA to the USB interface chip are listed below. Note that the FPGA shares some of its pins between the USB interface, the PS/2 interface and one pushbutton switch.
  • Page 36 2 and 3 of jumpers J29, J30, and J31, respectively. Along with the parallel port interface circuitry in the CPLD, these inverters make the XSV Board compatible with the GXSPORT and GXSLOAD software utilities. If your application requires direct access to these signal lines, then you can move the shunts on one or more of these jumpers to pins 1 and 2.
  • Page 37 17 (C3) Serial Port The CPLD handles the interface to the serial port. The four active lines of the serial port connect to general-purpose I/O pins on the CPLD as follows. Serial Port XC95108 CPLD Pin XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 38 6 – TRIG 7 – CCLK 9 – DONE 10 – TDI 11 – DIN 12 – TCK 13 – PROGRAM 14 – TMS 15 – INIT 16 – CLKI 17 – RST 18 – CLKO XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 39 J13 and J14 to connect the outputs from the voltage regulators to the rest of the XSV Board. We do not recommend the 9 VDC power input for general use! The 2.5V for the Virtex FPGA core logic can be generated on the XSV Board or supplied from an external source.
  • Page 40 The following tables list the pin numbers of the Virtex FPGA and the XC95108 CPLD along with the pin names of the other chips that they connect to. These connections correspond with the pin assignments in the user-constraint files VIRTEX.UCF and CPLD.UCF. XSV BOARD V1.1 MANUAL 9/21/2001...
  • Page 41 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker S3 (left) MCLK LRCK SCLK SDIN SDOUT VCCO VCCINT...
  • Page 42 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker /HSYNC /VSYNC /BLANK PIXELCLK A9 (right) A8 (right) A7 (right)
  • Page 43 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker PGCK LLCK D14 (right) D15 (right) /OE (right) A18 (right)
  • Page 44 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker VCCO VCCINT S5 (left) S3 (right) TRIG DIPSW8 S4 (right)
  • Page 45 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker S2 (left) S1 (left) /CE (left) A9 (left) A8 (left)
  • Page 46 Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog. Virtex FPGA CPLD LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker VCCO /OE (left) A18 (left) A17 (left) A16 (left)
  • Page 47 Connections Between the XC95108 CPLD and the Other XSV Board Components Virtex Flash Video Parallel Serial Prog. XC95108 CPLD FPGA LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker /LEDS CFG1 /RESET /RESET VCCINT /INIT DONE /PROGRAM CCLK...
  • Page 48 Connections Between the XC95108 CPLD and the Other XSV Board Components Virtex Flash Video Parallel Serial Prog. XC95108 CPLD FPGA LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker BAR8 BAR6 DIPSW1 A13 VCCO DIPSW2 A14 DIPSW3 A15...
  • Page 49 Connections Between the XC95108 CPLD and the Other XSV Board Components Virtex Flash Video Parallel Serial Prog. XC95108 CPLD FPGA LEDs Switches Ethernet Decoder RAMDAC Codec PS/2 Port Port Osc. Xchecker VCCO CFG0 MDDIS /LEDR /LEDT /LEDL VCCINT /LEDC...
  • Page 50 XSV Schematics The following pages show the detailed schematics for the XSV Board. XSV BOARD V1.1 MANUAL 9/21/2001...