Mbit Flash Ram - XESS XSV Manual

XC95108
CPLD

16 Mbit Flash RAM

An Intel 28F016S5 Flash RAM with 16 Mbits of storage (2M × 8) is connected to both the
Virtex FPGA and XC95108 CPLD as follows:
XC95108
CPLD
The CPLD and FPGA both have access to the Flash RAM. Typically, the CPLD will
program the Flash with data passed through the parallel or serial port. If the data is an
FPGA configuration bitstream then the CPLD can be configured to program the FPGA
with the Flash bitstream whenever the XSV Board is powered up. After power-up, the
FPGA can read and/or write the Flash. (Of course, the CPLD and FPGA have to be
programmed such that they do not conflict if both are trying to access the Flash.) The
Flash can be disabled by raising the /CE pin to Vcc in which case the I/O lines connected
to the Flash can be used for general-purpose communication between the FPGA and the
CPLD.
The pins of the FPGA and CPLD connected to the Flash RAM are listed below:
J24
Virtex
FPGA
8
21
Virtex
FPGA
12
J27
DS1075
External
reset
ce
oe
16 Mbit
we
rdy
Flash RAM
d
0 - 7
a
0 - 2 0
Clock