XESS XSV Manual page 7

RAMDAC with a 256-entry, 24-bit colormap that is used by the FPGA to output video
n
to a VGA monitor.
Stereo codec that lets the FPGA digitize and generate 0-50 KHz audio signals with up
n
to 20 bits of resolution.
10BASE-T/100BASE-TX Ethernet PHY that allows the FPGA to access a LAN at up
n
to 100 Mbps.
Two expansion headers interface the FPGA to external circuitry through 76 general-
n
purpose I/Os.
Four pushbuttons and one eight-position DIP switch provide general-purpose inputs to
n
the FPGA and CPLD.
Two LED digits and one LED bargraph let the FPGA and CPLD display status
n
information.
Mouse/keyboard PS/2 port gives the FPGA access to common PC input devices.
n
Dual USB port provides the FPGA with two independent serial I/O channels with
n
bandwidths of 1.5 to 12 Mbps.
Parallel/serial port interfaces let the CPLD send and receive data in a parallel or serial
n
format similar to a PC.
Xchecker cable interface allows downloading and readback of the FPGA
n
configuration.
ATX power connector or 9 VDC power jack lets the XSV Board receive power from a
n
standard ATX power supply or a 9 VDC power supply.
The location of these resources are indicated in the simplified view of the XSV Board
shown below. Each of these resources will be described in the following section.
6