XESS XSV Manual page 18

with the PIXELCLK generated by the FPGA. The FPGA lowers the /BLANK signal when
the pixels fall outside the desired visible area of the monitor screen.
The colormap of the RAMDAC is initialized by the FPGA using the D bus along with the
RS, /WR, and /RD signals. The 24-bit colormap entries are passed in groups of three
bytes over the eight-bit D bus synchronized by the /WR signal. The register-select signals
(RS0, RS1, RS2) select the staging register for writing the colormap. The contents of the
staging register are written into the colormap after the last byte of color information arrives
over the D bus, and then the internal colormap address is incremented to point to the next
entry.
The shunt placement to enable the FPGA to generate VGA signals directly or through the
RAMDAC is shown below.
J7 J6
Direct VGA
Shunt Setting
The pin assignments for the connection of the FPGA to the VGA signal generation circuitry
are shown below. Note that the FPGA shares some connections between the RAMDAC
and the chip which interfaces to the Ethernet (LXT970A). The RAMDAC pins are used to
load the colormap and should not be active except during system initialization. The other
connections are used for Ethernet data transmission and reception and are usually only
active after system initialization.
Direct
VGA Pin
/HSYNC
/VSYNC
RED0
RED1
GREEN0
GREEN1
BLUE0
BLUE1
J5
RAMDAC Virtex
Pin FPGA Pin
PIXELCLK 52
/HSYNC 48
/VSYNC 49
/BLANK 50
P0 70
P1 71
P2 72
P3 73
P4 74
P5 78
P6 79
P7 80
/RD 47
/WR 46
RS0 31
RS1 28
RS2 26
D0 42
D1 41
17
J7 J6 J5
RAMDAC
Shunt Setting
LXT970A
Function
TXD4
RX_ER
RX_DV
TXD0
TXD1