Xsv Overview; Xsv Board Features - XESS XSV Manual

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XSV Overview

The XSV Board brings you the power of the XILINX Virtex FPGA embedded in a
framework for processing video and audio signals. The XSV Board accepts Virtex FPGAs
from 50K to 800K gates in size. The XSV can digitize PAL, SECAM, or NTSC video with
up to 9-bits of resolution on the red, green, and blue channels and can output video
images through a 110 MHz, 24-bit RAMDAC. The FPGA can also process stereo audio
signals with up to 20 bits of resolution and a bandwidth of 50 KHz. Two independent
banks of 512K x 16 SRAM are provided for local buffering of signals and data.
The XSV Board has a variety of interfaces for communicating with the outside world:
parallel and serial ports, Xchecker cable, dual USB ports, PS/2 mouse and keyboard port,
and 10/100 Ethernet PHY layer interface. There are also two independent expansion
ports, each with 38 general-purpose I/O pins connected directly to the Virtex FPGA.
You can configure the XSV Board through a PC parallel port, serial port, Xchecker cable
or from a bitstream stored in the 16 Mbit Flash RAM. The Flash RAM can also store data
for use by the FPGA after configuration is complete.

XSV Board Features

The XSV Board includes the following resources:
n Programmable logic chips:
XILINX Virtex FPGA: Virtex FPGAs from 57 Kgates (XCV50) up to 888 Kgates
XILINX XC95108 CPLD: The CPLD is used to manage the configuration of the
Programmable oscillator that provides a clock signal to the FPGA and CPLD derived
n
form a 100 MHz base frequency.
16 Mbit Flash RAM that can store multiple configurations or general-purpose data for
n
the FPGA.
Two independent 512K x 16 SRAM banks used by the FPGA for general-purpose
n
data storage.
Video decoder that accepts NTSC/PAL/SECAM signals through an RCA jack or S-
n
video connector and outputs the digitized signal to the FPGA.
(XCV800) are compatible with the XSV Board. The Virtex FPGA is the main
repository of programmable logic on the XSV Board.
Virtex FPGA via the parallel port, serial port, or Flash RAM. The CPLD also
controls the configuration of the Ethernet PHY chip.
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