Ramdac And Vga Monitor Interface - XESS XSV Manual

RAMDAC and VGA Monitor Interface

The FPGA can generate a video signal for display on a VGA monitor either directly or
using a RAMDAC depending upon the arrangement of the shunts on jumpers J5, J6, and
J7.
p
5
p
4
p
3
p
2
p
1
p
0
8
Virtex
FPGA
8
When the FPGA is directly generating VGA signals, the lower six bits of the P bus provide
two-bits of red, green, and blue color information to a simple resistor-ladder DAC. The
outputs of the DAC are sent to a VGA monitor along with the horizontal and vertical sync
pulses (/HSYNC, /VSYNC) from the FPGA.
When the RAMDAC generates the VGA color signals, then the FPGA uses the full eight-
bit P bus to pass the index of the color for the current pixel. The index is used to lookup
the 24-bit color value (eight bits for the red, green, and blue components) stored in the
256-entry colormap of the RAMDAC chip. The transfers over the P bus are synchronized
SAA7113 Virtex
Pin FPGA Pin
VPO0
VPO1
VPO2
VPO3
VPO4
VPO5
VPO6
VPO7
SCL
SDA
p
0 - 7
blank
pixelclk
BT481A
rd
RAMDAC
wr
rs
0 - 2
d
0 - 7
116
117
118
125
126
127
128
130
114
115
r r g
0 1 0
J5
red
J6
green
blue
16
vsync
hsync
g b b
1 0 1
VGA
Connector
(J4)
red
green
J7
blue