Sram Banks - XESS XSV Manual

SRAM Banks

The FPGA has access to two independent banks of SRAM as shown below: Each SRAM
bank is organized as 512K × 16 bits. The FPGA pins connected to the SRAM banks are
shown in the accompanying table.
d
0 - 7
4 Mbit
ce
oe
SRAM
we
a
0 - 1 8
a
0 - 1 8
4 Mbit
ce
oe
SRAM
we
d
0 - 7
8
19
Virtex
FPGA
8
SRAM Pin Virtex
FPGA Pin
to Left
Bank
/CE 186
/OE 228
/WE 201
D0 202
D1 203
D2 205
D3 206
D4 207
D5 208
D6 209
D7 215
D8 216
D9 217
D10 218
D11 220
D12 221
D13 222
D14 223
D15 224
A0 200
8
19
8
Virtex
FPGA Pin
to Right
Bank
109
95
68
70
71
72
73
74
78
79
80
81
82
84
85
86
87
93
94
67
14
d
0 - 7
4 Mbit
ce
oe
SRAM
we
a
0 - 1 8
a
0 - 1 8
4 Mbit
ce
oe
SRAM
we
d
0 - 7