Pushbuttons And Eight-Position Dip Switch - XESS XSV Manual

Pushbuttons and Eight-Position DIP Switch

The XSV Board has a bank of eight DIP switches and four pushbuttons that are
accessible from the FPGA. The CPLD is also connected to the DIP switches and one of
the pushbuttons. When pressed, each pushbutton pulls the connected pin of the FPGA
and CPLD to ground. Otherwise, the pin is pulled high through a resistor. Likewise, each
DIP switch pulls the connected pin of the FPGA or CPLD to ground when it is closed or
ON. When the DIP switch is open or OFF, the pin is pulled high through a resistor.
When not being used, the DIP switches should be left in the open or OFF
configuration so the pins of the FPGA and CPLD are not tied to ground and can
freely move between logic low and high levels.
External
Clock
DIP
Switch
(SW6)
SW4
SW3
SW2
SW1
XC95108 Virtex
CPLD FPGA
The table below lists the connections from the FPGA and CPLD to the switches. The DIP
switches also share the same pins as the uppermost eight bits of the Flash RAM address
bus. If the Flash RAM is programmed with several FPGA bitstreams, then the DIP switch
can be used to select a particular bitstreams which will be loaded into the FPGA by the
CPLD on power-up.
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