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4
Virtex
4
FPGA
4
XC95108
CPLD
The FPGA enables the transmitter with TX_EN and sends bits on TXD
transmit clock (TX_CLK) generated by the PHY chip. The PHY chip is alerted to
transmission errors that occur in the MAC when the TX_ERR signal is asserted. The
FPGA also receives an indication when valid data has been received (RX_DV) and the
data (RXD
) in sync with the receiver clock (RX_CLK) from the PHY chip. Any reception
0-4
errors are indicated to the FPGA via the RX_ER signal. The CRS signal indicates when
the receiver is non-idle. The COL signal is asserted when data collides on the Ethernet.
The FPGA can disable the interface to the PHY chip by asserting the tristate control
(TRSTE). Otherwise, the FPGA passes management information to and from the PHY
chip over the serial data line (MDIO) in sync with a clock (MDC). the FPGA can be alerted
to changes in PHY chip status by the FDS/MDINT interrupt line.
The CPLD sets the static values on pins which control the configuration of the PHY chip.
Pins MF0-4 set the modes for auto-negotiation, repeating, symbol transmission,
scrambling, etc. Likewise, the configurations signals (CFG0-1) select the 10 Mbps or 100
Mbps operating speed of the PHY chip. MDDIS enables/disables the management
information interface. FDE selects either full-duplex or half-duplex communication mode.
The reset (/RESET) and power-down (PWRDWN) signals do exactly what they say.
The CPLD also gets receives the status outputs from the PHY chip that normally drive
LEDs. The outputs are active-low and indicate when 100 Mbps operation is selected
(/LEDS), the receiver is active (/LEDR), the transmitter is active (/LEDT), the link is active
(/LEDL), and a collision is detected (/LEDC). The CPLD can relay these signals to the
LEDs on the XSV Board if you wish to display the Ethernet status.
tx_err
tx_clk
tx_en
txd
0 - 4
rx_er
rx_clk
rx_dv
rxd
0 - 4
col
crs
trste
LXT970A
fds/mdint
Ethernet
mdio
mdc
mf
0 - 4
2
cfg
0 - 1
mddis
fde
reset
pwrdwn
leds
ledr
ledt
ledl
ledc
19
tpop
tpon
tpip
tpin
PHY
4-0
RJ45
Connector
(J3)
in sync with the
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