Parallel Port - XESS XSV Manual

Virtex
FPGA
The speed of the upper and lower USB ports is set by jumpers J19 and J18, respectively.
If the USB peripheral connected to the upper or lower port needs to draw power from the
XSV Board, then a shunt should be placed on jumper J17 or J16, respectively.
Lower = 1.5 Mbps
The connections of the FPGA to the USB ports are listed below:

Parallel Port

The CPLD handles the interface to the parallel port. The seventeen active lines of the
parallel port connect to general-purpose I/O pins on the CPLD.
Four of the parallel port lines also connect to the JTAG pins through which the CPLD is
programmed. The TCK signal clocks configuration data in through the TDI pin while the
J19
Upper = 12 Mbps
Dual USB
Port Pin
J17
V (upper)
J18
c c
D- (upper)
D+ (upper)
D- (lower)
D+ (lower)
V (lower)
c c
J16
J18
J19
Upper = 1.5 Mbps
Lower = 12 Mbps
Virtex
FPGA Pin
D- 9
D+ 10
D- 11
D+ 12
27
USB
Connector
(J15)
J18
J19