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The connections of the PHY chip to the FPGA and CPLD are listed below. Note that the
FPGA shares some connections between the PHY chip and the RAMDAC. The
RAMDAC pins are used to load the colormap and should not be active except during
system initialization. The PHY connections are used for data transmission and reception
and are usually only active after system initialization.
LXT970A
Pin
COL
CRS
TRSTE
TX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
RX_CLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
FDS/MDINT
MDC
MDIO
MDDIS
MF0
MF1
MF2
MF3
MF4
CFG0
CFG1
FDE
/RESET
/LEDS
/LEDR
/LEDT
/LEDL
/LEDC
Virtex
XC95108
FPGA Pin
CPLD Pin
23
21
24
210
25
27
42
41
40
39
31
213
26
28
38
36
35
34
33
18
19
20
94
91
90
89
87
86
93
2
92
3
1
95
96
97
99
20
RAMDAC
D0
D1
D2
D3
RS0
RS2
RS1
D4
D5
D6
D7
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