Programming The Interface; Downloading Virtex Configuration Bitstreams - XESS XSV Manual

Connect your external frequency source to connector J27. The clock frequency sent
q
to the CPLD and FPGA should now be external frequency ÷ DIVISOR.

Programming the Interface

The Virtex FPGA is the main repository of programmable logic on the XSV Board. The
CPLD manages the configuration of the FPGA via the parallel or serial ports or from the
Flash memory. Therefore, the CPLD must be configured so that it implements the
necessary interface. The CPLD stores its configuration in its internal non-volatile memory
so the interface is restored each time power is applied to the XSV Board.
The CPLD is configured with an interface as follows:
Remove power from the XSV Board.
q
q Remove the cable to the parallel port connector.
q Place a shunt on jumper J23.
Restore power to the XSV Board.
q
q Reconnect the cable to the PC parallel port.
q Enter the following command in a DOS window if you want to program the XSV Board
through the PC parallel port:
(The serial and Flash memory interfaces are not currently implemented.)
Wait for the interface programming to complete.
q
q Remove power and the parallel port cable from the XSV Board.
Remove the shunt on jumper J24.
q
Restore power and the parallel port cable to the XSV Board.
q
Now you can download Virtex configuration files into the FPGA of the XSV Board.

Downloading Virtex Configuration Bitstreams

Once the CPLD is programmed with the downloading interface circuit, you can download
bitstreams into the Virtex FPGA using the command:
where FILE.BIT is a configuration bitstream generated by the Xilinx implementation tools
for the particular type of Virtex FPGA on your XSV Board.
XSINTFC PARALLEL
XSLOAD FILE.BIT
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