Emif16 Signal Descriptions; Basic Block Diagram For Emif16 - Texas Instruments EMIF16 User Manual

2.1 EMIF16 Signal Descriptions

Chapter 2—Architecture
2.1 EMIF16 Signal Descriptions
2-2 KeyStone Architecture External Memory Interface (EMIF16) User Guide
A basic block diagram of the EMIF16 asynchronous interface is shown in
Table 2-1 below lists the asynchronous signals of the EMIF16 module.
Figure 2-1

Basic Block diagram for EMIF16

Table 2-1 EMIF16 Signal Descriptions
Pin
EMIFD [15:0]
EMIFA [23:0]
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFBE[1:0]
EMIFWAIT [1:0]
EMIFWE
EMIFOE
EMIFRnW
End of Table 2-1
EMIFD [15:0]
EMIFA [23:0]
EMIFCE [3:0]
EMIFBE [1:0]
External
Memory
EMIFWE
Interface
EMIFOE
(EMIF16)
EMIFWAIT [1:0]
EMIFRnW
Description
Data I/O. Input for data reads and output for data writes.
External address output.
External CE0 chip select. Active-low chip select for CE space 0.
External CE1 chip select. Active-low chip select for CE space 1.
External CE2 chip select. Active-low chip select for CE space 2.
External CE3 chip select. Active-low chip select for CE space 3.
Byte enables.
Used to insert wait states into the memory cycle.
Write enable - active low during a write transfer strobe period
Output enable-active low during the entire period of a read access.
Read-write enable
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Figure 2-1.
SPRUGZ3A—May 2011
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