Select Strobe Mode; Asynchronous Write Timing Diagram - Texas Instruments EMIF16 User Manual

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Figure 2-5

Asynchronous Write Timing Diagram

EMIFCE
EMIFBE[1:0]
EMIFA[23:0]
EMIFD[15:0 ]
EMIFOE
EMIFWE
EMIFRnW

2.5.5 Select Strobe Mode

SPRUGZ3A—May 2011
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Bus contention is addressed by having a programmable turnaround time inserted
between back-to-back accesses to the same or different CE spaces (See
turnaround cycles).
1: In case an asynchronous request cannot be serviced in a single
Note—
asynchronous access cycle, multiple cycles are needed to complete the single
read or write request. In this case, the EMIF16 enters the setup phase directly
without incurring turnaround cycles.
2: If the entire read or write access has completed and there are more
Note—
requests pending, the EMIF16 enters turnaround state and waits for
programmed turnaround cycles.
Figure 2-5 shows a write cycle initiated as described above. Refer to the device datasheet
for timing characteristics.
Write setup
The Select Strobe (SS) Mode is selected when the 'ss' bit in Async Wait Cycle Config
Register (AWCCR) is set to '1'. SS mode overrides the WE strobe mode when 'ss' = 1.
In SS mode, EMIFBE[1:0] act as byte enables. However the chip select EMIFCE behaves
as the strobe and is active only during the strobe period.
KeyStone Architecture External Memory Interface (EMIF16) User Guide
Write strobe Write hold
Byte enables
Address
Write data
2.5 ASRAM/NOR Flash Interface
Chapter 2—Architecture
Section 2.5.2 for
2-9