ADLINK Technology cPCI-7300A User Manual
  1. Manuals
  2. Brands
  3. ADLINK Technology Manuals
  4. I/O Systems
  5. cPCI-7300A
  6. User manual

ADLINK Technology cPCI-7300A User Manual

80mb ultra-high speed 32-ch digital i/o boards
Hide thumbs Also See for cPCI-7300A:
Table of Contents

Advertisement

Quick Links

Download this manual
cPCI-7300A/PCI-7300A
80MB Ultra-High Speed 32-CH
Manual Rev.
Revision Date:
Part No:
Advance Technologies; Automate the World.
Digital I/O Boards
User's Manual
2.01
December 21, 2006
50-11106-101

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the cPCI-7300A and is the answer not in the manual?

Questions and answers

Related Manuals for ADLINK Technology cPCI-7300A

Summary of Contents for ADLINK Technology cPCI-7300A

  • Page 1 80MB Ultra-High Speed 32-CH Digital I/O Boards User’s Manual Manual Rev. 2.01 Revision Date: December 21, 2006 Part No: 50-11106-101 Advance Technologies; Automate the World.
  • Page 2 Copyright 2006 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
  • Page 3 Getting Service from ADLINK Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance. ADLINK TECHNOLOGY INC. Web Site: http://www.adlinktech.com Sales & Service: Service@adlinktech.com TEL: +886-2-82265877 FAX: +886-2-82265717 Address: 9F, No. 166, Jian Yi Road, Chungho City,...

  • Page 5: Table Of Contents

    Table of Contents Table of Contents..............i List of Tables................. vii List of Figures ..............viii 1 Introduction ................ 1 Applications ................. 2 Features................2 Specifications............... 3 Software Support ..............5 Programming Library ............5 DAQ-LVIEW PnP: LabVIEW® Driver ......6 PCIS-VEE: HP-VEE Driver ..........
  • Page 6 3.10 ......PLX PCI-9080 DMA Control Registers 30 4 Operation Theory .............. 31 I/O Configuration..............31 Block Diagram..............32 Digital I/O Data Flow ............33 Input FIFO and Output FIFO..........34 Bus-mastering DMA............35 Scatter/gather DMA ............37 Clocking Mode ..............38 Starting Mode..............
  • Page 7 @ Description ............... 62 @ Syntax ..............62 @ Argument ..............62 @ Return Code ............. 63 _7300_DI_Mode ..............64 @ Description ............... 64 @ Syntax ..............64 @ Argument ..............64 @ Return Code ............. 64 _7300_DO_Mode .............. 65 @ Description ...............
  • Page 8 @ Description ............... 72 @ Syntax ..............72 @ Argument ..............72 @ Return Code ............. 72 5.14 _7300_DI_DMA_Start............73 @ Description ............... 73 @ Syntax ..............74 @ Argument ..............75 @ Return Code ............. 75 5.15 _7300_DI_DMA_Status ............. 77 @ Description ...............
  • Page 9 @ Argument ..............84 @ Return Code ............. 84 5.22 _7300_DO_PG_Stop............86 @ Description ............... 86 @ Syntax ..............86 @ Argument ..............86 @ Return Code ............. 86 5.23 _7300_DI_Timer ..............87 @ Description ............... 87 @ Syntax ..............87 @ Argument ..............
  • Page 10 Warranty Policy ..............99 Table of Contents...

  • Page 11: List Of Tables

    List of Tables Table 2-1: Connector Pin Assignment ........12 Table 3-1: I/O Port Base Address ..........18 Table 4-1: I/O Configuration ............ 31 Table 5-1: Data Types ............. 58 List of Tables...
  • Page 12 List of Figures Figure 2-1: PCI-7300A Layout Diagram........9 Figure 2-2: cPCI-7300A Layout Diagram ........10 Figure 2-3: CN1 Pin Assignment..........14 Figure 4-1: Block diagram ............32 Figure 4-2: Data flow of digital input........... 33 Figure 4-3: Data flow of digital output ........33 Figure 4-4: Maximum data throughput ........

  • Page 13: Introduction

    Introduction The cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed dig- ital I/O card, it consists of 32 digital input or output channel. High performance designs and the state-of-the-art technology make this card to be ideal for high speed digital input and output applica- tions.

  • Page 14: Applications

    1.1 Applications Interface to high-speed peripherals High-speed data transfers from other computers Automated test equipment (ATE) Electronic and logic testing Interface to external high-speed A/D and D/A converter Digital pattern generator Waveform and pulse generation Parallel digital communication 1.2 Features The PCI-7300A Ultra-High Speed DIO card provides the following advanced features: 32 digital input/output channels...

  • Page 15: Specifications

    1.3 Specifications Digital I/O (DIO) Numbers of Channel: 32 TTL compatible inputs and/or out- puts Device: IDT 74FCT373 I/O Configurations: 16 DI & 16 DO 32 DI 32 DO Input Voltage: Low: Min. 0V; Max. 0.8V High: Min. +2.0V Input Load: Terminator OFF: ±...
  • Page 16 DMA Transfer count: No limitation for chaining mode (scatter/gather) DMA Max. Transfer rate: DO: 80M Bytes/sec: 32-bit output @ 20 MHz DI: 80M Bytes/sec: 32-bit input @ 20 MHz Programmable Counter: Device: 82C54-10 Digital Input Pacer: 20MHz, 10MHz, or clock output of Timer Digital Output Pacer: 20MHz, 10MHz, or clock output of Timer #1 General Specifications...

  • Page 17: Software Support

    1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to built-up a system. We not only pro- vide programming library such as DLL for many Windows sys- tems, but also provide drivers for software packages such as LabVIEW®, HP VEETM, DASYLabTM, and so on.

  • Page 18: Daq-Lview Pnp: Labview® Driver

    DAQ-LVIEW PnP: LabVIEW® Driver DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW® software package. The DAQ-LVIEW PnP supports Windows 2000/XP. The LabVIEW® drivers are free shipped with the board. You can install and use them without license.

  • Page 19: Installation

    Installation This chapter describes how to install the cPCI/PCI-7300A. At first, the contents in the package and unpacking information that you should be careful are described. Because the PCI-7300A is fol- lowing the PCI design philosophy, it is no more jumpers and DIP switches setting for configuration.

  • Page 20: Unpacking

    2.2 Unpacking Your cPCI/PCI-7300A card contains sensitive electronic compo- nents that can be easily damaged by static electricity. The card should be placed on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage.

  • Page 21: Pci-7300A's Layout

    2.4 PCI-7300A's Layout Figure 2-1: PCI-7300A Layout Diagram Installation...

  • Page 22: Figure 2-2: Cpci-7300A Layout Diagram

    Figure 2-2: cPCI-7300A Layout Diagram Installation...

  • Page 23: Hardware Installation Outline

    2.5 Hardware Installation Outline PCI configuration The PCI cards (or CompactPCI cards) are equipped with plug and play PCI controller, it can request base addresses and interrupt according to PCI standard. The system BIOS will install the system resource based on the PCI cards’ configura- tion registers and system parameters (which are set by system BIOS).

  • Page 24: Connector Pin Assignment

    2.6 Connector Pin Assignment The PCI-7300A comes equipped with one 100-pin SCSI type con- nector (CN1) located on the rear mounting plate. The pin assign- ment of CN1 is illustrated in the Figure 2-3. Legend: Signa Pins Signal Name Signal Type Description Direction Ground –...
  • Page 25 Signa Pins Signal Name Signal Type Description Direction DI TRIG – can be used to control the DITRIG CONTROL start of data acquisition in all DI modes. AUX DI 3…0 – can be used as extra 78…81 AUXDI3…0 DATA input data or can be used as extra con- trol signals.

  • Page 26: Figure 2-3: Cn1 Pin Assignment

    Figure 2-3: CN1 Pin Assignment Installation...

  • Page 27: Wiring And Termination

    Wiring and Termination Transmission line effects and environment noise, particularly on clock and control lines, can lead to incorrect data transfers if you do not take care when running signal wires to and from the devices. Take the following precautions to ensure a uniform transformation line and minimize noise pickup: 1.

  • Page 28: Termination Board Supporting

    2.8 Termination Board Supporting The cPCI/PCI-7300A can be connected with two daughter boards: DIN-100S or DIN-502S. The functionality and connections are specified as follows. Connect with DIN-100S The DIN-100S is a direct connection for the add-on card that is equipped with SCSI-100 connector. User can connect this daugh- ter board by a 100-pin SCSI type cable (ACL-102100) to the cPCI/ PCI-7300A.

  • Page 29: Registers

    Registers In this chapter, the registers’ format of the cPCI/PCI-7300A is described. Please note that the registers’ map of the PCI-7300A Rev.B is different from the PCI-7300A Rev.A This information is quite useful for the programmers who wish to handle the card by low-level programming. In addition, users can realize how to use software driver to manipulate this card after understanding the registers' structure of the cPCI/PCI-7300A The cPCI/PCI-7300A functions as a 32-bit PCI master device on...

  • Page 30: I/O Port Base Address

    3.1 I/O Port Base Address The registers of the cPCI/PCI-7300A are shown in Table 3.1. The base address of these registers is also assigned by the PCI P&P BIOS. The assigned base address is stored at offset 18h of the PCR.
  • Page 31 Legend: DI_CSR: Digital input control & status register DO_SCR: Digital output control & status register AUX_DIO: Auxiliary digital I/O port INT_CSR: Interrupt control and status register DI_FIFO: DI FIFO direct access port DO_FIFO: DO FIFO direct access port FIFO_CR: FIFO almost empty/full programming register POL_CTRL: Polarity control register for the control signals Caution: I/O port is 32-bit width...

  • Page 32: Di_Csr: Di Control & Status Register

    3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register. Address: BASE + 00 Attribute: READ/WRITE Data Format: Bit # 3~0 DI_HND_SHK DI_CLK_SEL DI_32 Bit # 7~4 PA_TERM_OFF DI_WAIT_TRIG -- (1) Bit # 11~8 DI_FIFO_FULL DI_OVER DI_FIFO_CLR DI_EN...
  • Page 33 DI_EN (R/W) 0: Disable digital inputs 1: Enable digital inputs DI_FIFO_CLR (R/W) 0: No effect 1: Clear digital input FIFO. If both PORTA and PORTB are configured as inputs, both FIFO will be cleared. Always get 0 when read. DI_OVER (R/W) 0: DI FIFO does not full during input sampling 1: DI FIFO full during input sampling, some input data was lost, write “1”...

  • Page 34: Do_Csr: Do Control & Status Register

    3.3 DO_CSR: DO Control & Status Register Digital input control and status checking is done by this register. Address: BASE + 04 Attribute: READ/WRITE Data Format: Bit # 3~0 DO_WAIT_NAE DO_MODE DO_32 Bit # 7~4 PG_STOP_TRIG PB_TERM_OFF DO_WAIT_TRG PAT_GEN Bit # 11~8 DO_FIFO_FULL DO_UNDER DO_FIFO_CLR...
  • Page 35 DO_WAIT_TRIG (R/W) 0: start output data immediately 1: delay output data until DOTRIG is actived PB_TERM_OFF (R/W) 0: PORTB terminator ON 1: PORTB terminator OFF PG_STOP_TRIG (R/W) 0: no effect 1: Stop pattern generation when DOTRIG is deasserted DO_EN (R/W) 0: Disable digital outputs 1: Enabled digital outputs DO_FIFO_CLR (R/W)

  • Page 36: Auxiliary Digital I/O Register

    3.4 Auxiliary Digital I/O Register Auxiliary 4-bit digital inputs and 4-bit digital outputs Address: BASE + 08 Attribute: READ/WRITE Data Format: Bit # 3~0 DO_AUX_3 DO_AUX_2 DO_AUX_1 DO_AUX_0 Bit # 7~4 DI_AUX_3 DI_AUX_2 DI_AUX_1 DI_AUX_0 Bit # 31~8 Don’t Care This auxiliary digital I/O is controlled by porgram I/O only.

  • Page 37: Int_Csr: Interrupt Control And Status Register

    3.5 INT_CSR: Interrupt Control and Status Register The interrupt of PCI-7300A is controlled and status is checked through this register. Address: BASE + 0x0C Attribute: READ/WRITE Data Format: Bit # 3~0 T2_INT AUXIO_INT T2_EN AUXDI0_EN Bit # 7~4 Reserved Reserved Bit # 31~8 Don’t Care AUXDI_EN (R/W)

  • Page 38: Di_Fifo: Di Fifo Direct Access Port

    3.6 DI_FIFO: DI FIFO direct access port The digital input FIFO data can be accessed through this port directly. Address: BASE + 0x10 Attribute: READ/WRITE Data Format: Bits 7 6 5 4 3 2 1 0 Bit # 7~0 DI_FIFO_8 Bit # 15~8 DI_FIFO_16 Bit # 31_16...

  • Page 39: Do_Fifo: Do External Data Fifo Direct Access Port

    3.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this port directly. Address: BASE + 0x0C Attribute: READ/WRITE Data Format: Bits 7 6 5 4 3 2 1 0 Bit # 7~0 DO_FIFO_8 Bit # 15~8 DO_FIFO_16...

  • Page 40: Fifo_Cr: Fifo Almost Empty/Full Register

    3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almost empty/full flag. Address: BASE + 0x018 Attribute: WRITE Only Data Format: Bits 7 6 5 4 3 2 1 0 Bit 15~0 PB_PAE_PAF Bit 31_16 PA_PAE_PAF PB_PAE_PAF (WO) Programmable almost empty/full threshold of PORTB FIFO, 2...

  • Page 41: Pol_Cntrl: Control Signal Polarity Control Register

    3.9 POL_CNTRL: Control Signal Polarity Control Register The register is used to control the control signals’ polarity. control signals include DI_REQ, DI_ACK, DI_TRG, DO_REQ, DO_ACK and DO_TRG. Please note that this register is for PCI- 7300A Rev.B and cPCI-7300 only. Address: BASE + 0x1C Attribute: READ/WRITE Data Format:...

  • Page 42: Plx Pci-9080 Dma Control Registers

    3.10 PLX PCI-9080 DMA Control Registers The registers of bus-mastering DMA as well as the control and status registers of PCI-bus interrupts are built in the PLX PCI-9080 ASIC. Users can refer to the manual of PLX PCI-9080 for detailed information.

  • Page 43: Operation Theory

    Operation Theory This chapter provides the detailed operation information for the cPCI/PCI-7300A, including I/O configuration, block diagram, input/ output FIFO, bus-mastering DMA, scatter/gather, clocking mode, starting mode, termination, I/O transfer mode, and auxiliary digital I/O. 4.1 I/O Configuration The 32-bit I/O data path of PCI-7300A can be configured as 8-bit, 16-bit, or 32-bit, the possible configuration modes are listed as fol- lows.

  • Page 44: Block Diagram

    DO0:output LSB, DO31:output MSB. LSB: Least Significant Bit, MSB: Most Significant Bit 4.2 Block Diagram Figure 4-1 shows the block diagram of the cPCI/PCI-7300A, it includes the I/O registers, two 16K FIFOs, auxiliary DIO, active terminators, and so on. Figure 4-1: Block diagram 16 Digital I/O Port, it can be set as terminated PORTA: mode or non-terminated mode...

  • Page 45: Digital I/O Data Flow

    4.3 Digital I/O Data Flow When applying digital input functions, the data will be sampled into the input FIFO periodically as we configured and then transfer to the system memory by the bus mastering DMA of the PCI Bridge. Figure 4-2 show the data flow of the 16-bit digital input operation. Figure 4-2: Data flow of digital input On the other hand, Figure 4-3 shows the data flow of 16-bit digital output operation.

  • Page 46: Input Fifo And Output Fifo

    4.4 Input FIFO and Output FIFO Due to the data transfer rate between external devices and the cPCI/PCI-7300A is independent from that between cPCI/PCI- 7300A and PCI bus. Two 16K words FIFO are provided to be I/O buffers. For digital input operation, data is sampled and transferred to the input FIFO.

  • Page 47: Bus-Mastering Dma

    do chaining mode DMA which will generate the desired pat- tern repetitively. 4.5 Bus-mastering DMA Digital I/O data transfer between PCI-7300A and PC’s system memory is through bus mastering DMA, which is controlled by PCI bridge chip PLX PCI-9080. The PCI bus master means the device requires fast access to the bus or high data throughput in order to achieve good performance.
  • Page 48 transfer the maximum data size as they have on their system memory. However, if the data should be real-time saved to the hard-disk rather than memory, the bottleneck would be the data transfer rate of the hard-disk driver. Operation Theory...

  • Page 49: Scatter/Gather Dma

    4.6 Scatter/gather DMA The PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the users to transfer a large amount of data by linking the all memory blocks into a continuous linked list. In the multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on.

  • Page 50: Clocking Mode

    4.7 Clocking Mode The data input to or output from the FIFO is operated in a specific rate. The specific sampling rate or the pacer rate can be program- mable by software, by external clock, or by easy handshaking pro- tocol.
  • Page 51 tion of DI-ACK. If the external device follows the rule, there would be no data lost due to FIFO overrun. 3. Handshaking: For the digital input, through DI-REQ input signal from external device and DI-ACK output sig- nal to the external deviec, the digital input can have sim- ple handshaking data transfer.

  • Page 52: Starting Mode

    4.8 Starting Mode Users can also control the starting mode of digital input and output by external signals (DITRIG and DOTRIG) with the software pro- grams. The trigger modes includes NoWait, WaitTRIG, WaitFIFO, and WaitBoth. 1. NoWait: The data transfer is started immediately when a I/O transfer command is issued.

  • Page 53: Digital Input Operation Mode

    4.10 Digital Input Operation Mode Digital Input DMA in Internal Clock Mode There are three sources to trigger digital input in the internal clock mode: 20MHz, 10MHz, and programmable timer 82C54. There are three counters in 82C54, where the counter 0 is used for sam- pling clock source for digital input.
  • Page 54 The operation flow is show as below: Note: When the DMA function of digital input starts, the input data will be stored in the FIFO of the cPCI/PCI-7300A. The data then transfer to system memory if PCI bus is available. If the speed of translation from external device to the FIFO on board is higher than that from FIFO to system memory or the PCI bus is busy for a long time, the FIFO become full and...

  • Page 55: Digital Input Dma In External Clock Mode

    than the on-board FIFO buffer time. The FIFO size is 16K sample, so it has 1.6 ms buffer time for 10MHz sampling rate if the FIFO is empty when last DMA is complete. Users may try different DMA buffer size to see how the DMA buffer size affects the overall performance.

  • Page 56: Figure 4-7: Direq As Input Data Strobe (Rising Edge Active)

    The operation flow is show as below: The followings are timing diagrams of the DI-REQ and the input data. The active edge of DI-REQ can be programmed by the func- tion 5.5. Figure 4-7: DIREQ as input data strobe (Rising Edge Active) Operation Theory...

  • Page 57: Digital Input Dma In Handshaking Mode

    Figure 4-8: DIREQ as input data strobe (Falling Edge Active) Note: From the timing diagram of external clock mode, the maxi- mum frequency can be up to 40MHz. However, users should note that when the sampling frequency of digital input is higher than the PCI bus bandwidth (33Mhz), or the band- width of chipset (30Mhz typically) from PCI bus to system memory.
  • Page 58 fer.The operations sequence of digital input with handshaking are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the input sampling rate as handshaking mode. Connect the handshaking signals of the external device to input pin DI-REQ and output pin DI-ACK.

  • Page 59: Continuous Digital Input

    The following figure shows the timing requirement of the hand- shaking mode digital input operation. Figure 4-9: DIREQ & DIACK Handshaking Note: DIREQ must be asserted until DIACK asserts, DIACK will be asserted until DIREQ de-asserted. Continuous Digital Input If the digital input operation still active after the competition of the previous DMA transfer and do not clear the data in the input FIFO when the next DMA starts, the cPCI/PCI-7300A can achieve the continuous digital input function in a high-speed sampling rate.
  • Page 60 and remove the unnecessary processes in your applica- tion programs. 3. When high-speed sampling frequency is applied, the larger block size will improve the efficiency of DMA transferring, and probability of overrun in the DMA pro- cess will be reduced. 4.

  • Page 61: Digital Output Operation Mode

    4.11 Digital Output Operation Mode Digital Output DMA in Internal Clock Mode There are three sources to trigger digital output: 20MHz, 10MHz, and programmable timer 82C54. There are three counters in 82C54, where the counter 1 is used timer pacer for digital output. The operations sequence of digital output with internal clock are listed: 1.

  • Page 62: Digital Output Dma In Handshaking Mode

    As the data output in the internal clock mode, the DOREQ signal could be use as the output strobe to indicate the output operation to the external device. The timing diagram of the DOREQ is shown as follows: Figure 4-10: DOREQ as output data strobe Digital Output DMA in Handshaking Mode For digital output, through DO-REQ output signal and DO-ACK input signal, the digital output can have simple handshaking data...
  • Page 63 The operations sequence of digital output in handshaking mode are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the output clock mode as handshaking mode. Connect the handshaking signals of the external device to output pin DO-REQ and input pin DO-ACK.

  • Page 64: Digital Output Dma In Burst Handshaking Mode

    The timing diagram of the DOREQ and DOACK in the DO hand- shaking mode is shown as follows: Figure 4-11: DOREQ & DOACK Handshaking Note: DOACK must be deserted before DOREQ asserts, DOACK can be asserted any time after DOREQ asserts, DOREQ will be reasserted after DOACK is asserted.
  • Page 65 The operations sequence of digital output in burst handshaking mode are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the output clock as burst handshaking mode and decide the timer pacer rate to be 20Mhz, 10Mhz, or the output of 82C54 timer 1.
  • Page 66 The operation flow is show as below: Note: When the DMA function of digital output starts, the output data will transfer to the output FIFO of cPCI/PCI-7300A when PCI bus is available. If the speed of translation from the FIFO on board to the external device is higher than that from system memory to the output FIFO or the PCI bus is busy for a long time, the FIFO become empty and under-run situation occurs after the next data being read from the out-...

  • Page 67: Pattern Generator

    Pattern Generator The digital data is output to the peripheral device periodically based on the clock signals occur at a constant rate. The digital pattern are stored in the cPCI/PCI-7300A’s on-board FIFO with the length of pattern less than or equal to 16K samples. The operations sequence of pattern generator are listed: 1.

  • Page 68: Auxiliary Dio

    4.12 Auxiliary DIO The cPCI/PCI-7300A also includes four auxiliary digital inputs and four digital outputs, which can be applied to achieve the simple I/O functions. Users can refer to the functions 5.8 ~5.11 for the detailed information. Operation Theory...

  • Page 69: C++ Libraries

    C/C++ Libraries This chapter describes the software library for operating this card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included in ADLINK CD, for the descriptions of the Windows 98/NT/2000 DLL functions.

  • Page 70: Programming Guide

    5.2 Programming Guide Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using full-names to represent the func- tions' real meaning. The naming convention rules are: In DOS Environment: _{hardware_model}_{action_name}. e.g. _7300_Initial(). functions PCI-7300A driver with...

  • Page 71: 7300_Initial

    5.3 _7300_Initial @ Description A PCI-7300A card is initialized according to the card number. Because the cPCI/PCI-7300A is PCI bus architecture and meets the plug and play design, the IRQ and base address (pass- through address) are assigned by system BIOS directly. Every cPCI/PCI-7300A card has to be initialized by this function before calling other functions.

  • Page 72: Return Code

    irq_no:system will give an available interrupt number to this card automatically. pci_master:TRUE: BIOS enabled PCI bus mastering FALSE: BIOS did not enable PCI bus mastering @ Return Code NoError, PCICardNumErr PCIBiosNotExistPCICardNotExist PCIBaseAddrErr C/C++ Libraries...

  • Page 73: 7300_Close

    5.4 _7300_Close @ Description Close a previously initialized PCI-7300A card. @ Syntax Visual C/C++ (Windows 95) int W_7300_Close (int card_number) Visual Basic (Windows 95) W_7300_Close (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_Close (int card_number) @ Argument card_number:The card number of the PCI-7300A card. @ Return Code NoError PCICardNumErr...

  • Page 74: 7300_Configure

    5.5 _7300_Configure @ Description Set the port DI/O configuration, terminator control, and control sig- nal polarity for the PCI-7300A card. @ Syntax Visual C/C++ (Windows 95) int W_7300_Configure (int card_number, int dio_config, int term_cntrl, int cntrl_pol) Visual Basic (Windows 95) W_7300_Configure (ByVal card_number As Long, ByVal dio_config As Long, ByVal term_cntrl As Long, ByVal cntrl_pol As Long) As Long...

  • Page 75: Return Code

    PAON_PBOFF: PORTA terminator ON, PORTB terminator PAON_PBON: PORTA terminator ON, PORTB terminator Note: term_cntrl is used to control the ON/OFF of the active termi- nators, not terminal power output: TERMPER) cntrl_pol:The polarity configuration. This argument is an inte- ger expression formed from one or more of the manifest constants defined in 7300.h.

  • Page 76: 7300_Di_Mode

    5.6 _7300_DI_Mode @ Description Set the clock mode and start mode for the PCI-7300A DI opera- tion. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_Mode (int card_number, int clk_mode, int start_mode) Visual Basic (Windows 95) W_7300_DI_Mode (ByVal card_number As Long, ByVal clk_mode As Long, ByVal start_mode As Long) As Long C/C++ (DOS)

  • Page 77: 7300_Do_Mode

    5.7 _7300_DO_Mode @ Description Set the clock mode and start mode for the PCI-7300A DO opera- tion. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_Mode (int card_number, int clk_mode, int start_mode, int fifo_threshold) Visual Basic (Windows 95) W_7300_DO_Mode (ByVal card_number As Long, ByVal clk_mode As Long, ByVal start_mode As Long, ByVal fifo_threshold As Long) As Long C/C++ (DOS)

  • Page 78: Return Code

    DO_WAIT_BOTH: delay output data until DOTRIG is active and FIFO is not almost empty. fifo_threshold:programmable almost empty threshold of both PORTB FIFO and PORTA FIFO (if PORTA is set as output). It is avaliavle only when start_mode is DO_WAIT_FIFO @ Return Code NoError PCICardNumErr PCICardNotInit...

  • Page 79: 7300_Aux_Di

    5.8 _7300_AUX_DI @ Description Read data from auxiliary digital input port. You can get all 4 bits input data by using this function. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DI (int card_number, int *aux_di) Visual Basic (Windows 95) W_7300_AUX_DI (ByVal card_number As Long, aux_di As Long) As Long C/C++ (DOS) int _7300_AUX_DI (int card_number, int *aux_di)

  • Page 80: 7300_Aux_Di_Channel

    5.9 _7300_AUX_DI_Channel @ Description Read data from auxiliary digital input channel. There are 4 digital input channels on the PCI-7300A auxiliary digital input port. When performs this function, the auxiliary digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.

  • Page 81: 7300_Aux_Do

    5.10 _7300_AUX_DO @ Description Write data to auxiliary digital output port. There are 4 auxiliary dig- ital outputs on the PCI-7300A. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DI (int card_number, int do_data) Visual Basic (Windows 95) W_7300_AUX_DI (ByVal card_number As Long, ByVal do_data As Long) As Long C/C++ (DOS) int _7300_AUX_DI (int card_number, int do_data)

  • Page 82: 7300_Aux_Do_Channel

    5.11 _7300_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are 4 aux- iliary digital output channels on the PCI-7300A. When performs this function, the digital output data is written to the corresponding channel. * channel means each bit of digital output port. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DO_Channel (int card_number, int...

  • Page 83: 7300_Alloc_Dma_Mem

    5.12 _7300_Alloc_DMA_Mem @ Description Contact Windows 95 system to allocate a memory for DMA trans- fer. This function is only available in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Alloc_DMA_Mem (U32 buf_size, HANDLE *memID, U32 *linearAddr) Visual Basic (Windows 95) W_7300_Alloc_DMA_Mem (ByVal buf_size As Long, memID As Long, linearAddr As Long) As Long @ Argument...

  • Page 84: 7300_Free_Dma_Mem

    5.13 _7300_Free_DMA_Mem @ Description Deallocate a system DMA memory under the Windows 95 envi- ronment. This function is only available in the Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Free_DMA_Mem (HANDLE memID) Visual Basic (Windows 95) W_7300_Free_DMA_Mem (ByVal memID As Long ) As Long @ Argument memID:The memory ID of the system DMA memory to deallocate.

  • Page 85: 7300_Di_Dma_Start

    5.14 _7300_DI_DMA_Start @ Description The function will perform digital input by DMA data transfer. It will take place in the background which will not stop until the N-th input data is transferred or your program execute the _7300_DI_DMA_Abort function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _7300_DI_DMA_Status.

  • Page 86: Syntax

    data transfer continually tests if any data in the FIFO and then blocks transfer, the system will continuously loop until the conditions are satisfied again but will not exit the block transfer cycle if the block count is not complete. If there is momentarily no input data, the PCI-7300A will relinquish the bus temporarily but returns immediately when more input data appear.

  • Page 87: Argument

    @ Argument card_number:The card number of the PCI-7300A card. mode (DOS):CHAIN_DMA: chaining DMA mode. By using the scatter-gather capability of PCI-7300A, the input data is put to sev- eral buffers which chained together. NON_CHAIN_DMA: The input data is stored in a block of contiguous memory.
  • Page 88 PCICardNotInit DMATransferNotAllowed InvalidDIOCount BufNotDWordAlign DMADscrBadAlign C/C++ Libraries...

  • Page 89: 7300_Di_Dma_Status

    5.15 _7300_DI_DMA_Status @ Description Since the _7300_DI_DMA_Start function is executed in back- ground, you can issue this function to check its operation status. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Status (int card_number, int *status) Visual Basic (Windows 95) W_7300_DI_DMA_Status (ByVal card_number As Long, status As Long) As Long C/C++ (DOS) int _7300_DI_DMA_Status (int card_number, int...

  • Page 90: 7300_Di_Dma_Abort

    5.16 _7300_DI_DMA_Abort @ Description This function is used to stop the DMA DI operation. After executing this function, the DMA transfer operation is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Abort (int card_number) Visual Basic (Windows 95) W_7300_DI_DMA_Abort (ByVal card_number As Long ) As Long C/C++ (DOS) int _7300_DI_DMA_Stop (int card_number)

  • Page 91: 7300_Getoverrunstatus

    5.17 _7300_GetOverrunStatus @ Description When you use _7300_DI_DMA_Start to input data, the input data is stored in the FIFO of PCI controller. The data then transfer to memory through PCI-bus if PCI-bus is available. If the FIFO is full and next data is written to the FIFO, overrun situation occurs. Using this function to check overrun status.

  • Page 92: 7300_Do_Dma_Start

    5.18 _7300_DO_DMA_Start @ Description The function will perform digital output N times with DMA data transfer. It will takes place in the background which will not be stop until the Nth conversion has been completed or your program exe- cute _7300_DO_DMA_Abort function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _7300_DO_DMA_Status.

  • Page 93: Return Code

    count:For non-chaining mode, this is the total number of digital output data in double-words (4-byte). The value of count can not exceed 2^21 (about 2 million). For chaining mode, please set this argument as 0. The number of digital output is determined by the information in DMA descriptor nodes.

  • Page 94: 7300_Do_Dma_Status

    5.19 _7300_DO_DMA_Status @ Description Since the _7300_DO_DMA_Start function is executed in back- ground, you can issue the function _7300_DO_DMA_Status to check its operation status. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_DMA_Status (int card_number, int *status) Visual Basic (Windows 95) W_7300_DO_DMA_Status (ByVal card_number As Long, status As Long) As Long C/C++ (DOS)

  • Page 95: 7300_Do_Dma_Abort

    5.20 _7300_DO_DMA_Abort @ Description This function is used to stop the DMA DO operation. After execut- ing this function, the _7300_DO_DMA_Start function is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_DMA_Abort (int card_number) Visual Basic (Windows 95) W_7300_DO_DMA_Abort (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_DO_DMA_Abort (int card_number)

  • Page 96: 7300_Do_Pg_Start

    5.21 _7300_DO_PG_Start @ Description The function will perform pattern generation with the data stored in buff_ptr. It will takes place in the background which will not be stop until your program execute _7300_DO_PG_Stop function to stop the process. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_PG_Start (int card_number, void *buff_ptr, U32 count)
  • Page 97 DMADscrBadAlign C/C++ Libraries...

  • Page 98: 7300_Do_Pg_Stop

    5.22 _7300_DO_PG_Stop @ Description This function is used to stop the pattern generation operation. After executing this function, the _7300_DO_PG_Start function is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_PG_Stop (int card_number) Visual Basic (Windows 95) W_7300_DO_PG_Stop (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_DO_PG_Stop (int card_number)

  • Page 99: 7300_Di_Timer

    5.23 _7300_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. Timer pacer frequency = 10Mhz / C0. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_Timer (int card_number, U16 c0) Visual Basic (Windows 95) W_7300_DI_Timer (ByVal card_number As Long, ByVal c0 As Integer) As Long C/C++ (DOS)

  • Page 100: 7300_Do_Timer

    5.24 _7300_DO_Timer @ Description This function is used to set the internal timer pacer for digital out- put. Timer pacer frequency = 10Mhz / C1. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_Timer (int card_number, U16 c1) Visual Basic (Windows 95) W_7300_DO_Timer (ByVal card_number As Long, ByVal c1 As Integer) As Long C/C++ (DOS)

  • Page 101: 7300_Int_Timer

    5.25 _7300_Int_Timer @ Description This function is used to set Counter #2. @ Syntax Visual C/C++ (Windows 95) int W_7300_Int_Timer (int card_number, U16 c2) Visual Basic (Windows 95) W_7300_Int_Timer (ByVal card_number As Long, ByVal c2 As Integer) As Long C/C++ (DOS) int _7300_Int_Timer (int card_number, U16 c2) @ Argument card_number:The card number of the PCI-7300A card.

  • Page 102: 7300_Get_Sample

    5.26 _7300_Get_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this function to access the index-th data in input DMA buffer. This function is only available in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Get_Sample (U32 linearAddr, U32 index, U32 *data_value, U32 portWidth) Visual Basic (Windows 95)

  • Page 103: 7300_Set_Sample

    5.27 _7300_Set_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this function to write the output data to the index-th position in output DMA buffer. This function is only avail- able in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Set_Sample (U32 linearAddr, U32 index,...

  • Page 104: 7300_Getunderrunstatus

    5.28 _7300_GetUnderrunStatus @ Description When you use _7300_DO_DMA_Start to output data, the output data is read from the FIFO on the cPCI/PCI-7300A. If the FIFO becomes empty and next data is read from the FIFO, underrun sit- uation occurs. Using this function to check underrun status. @ Syntax Visual C/C++ (Windows 95) int W_7300_GetUnderrunStatus (int card_number,...

  • Page 105: Appendix

    Appendix 8254 Programmable Interval Timer Note: The material of this section is adopted from “Intel Micropro- cessor and Peripheral Handbook Vol. II --Peripheral” The Intel (NEC) 8254 The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz.
  • Page 106 Control Byte: (Base + 7, Base + 11) SC1 SC0 RL1 RL0 M2 M1 M0 BCD SC1 & SC1 - Select Counter (Bit7 & Bit 6) SC1 SC0 COUNTER ILLEGAL RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4) RL1 RL0 OPERATION COUNTER LATCH...

  • Page 107: Mode Definition

    2. The count of the BCD counter is from 0 up to 99,999. Mode Definition In 8254, there are six different operating modes can be selected. They are: Mode 0: Interrupt on terminal count The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will count.
  • Page 108 The gate input when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus, the gate input can be used to synchronized by software. When this mode is set, the output will remain high until after the count register is loaded.
  • Page 109 Mode 5: Hardware Triggered Strobe. The counter will start counting after the rising edge of the trig- ger input and will go low for one clock period when the terminal count is reached. The counter is re-triggerable. the output will not go low until the full count after the rising edge of any trigger.
  • Page 110 Appendix...
  • Page 111 Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the follow- ing carefully. 1. Before using ADLINK’s products please read the user man- ual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA appli- cation form which can be downloaded from: http:// rma.adlinktech.com/policy/.
  • Page 112 3. Our repair service is not covered by ADLINK's guarantee in the following situations: Damage caused by not following instructions in the User's Manual. Damage caused by carelessness on the user's part dur- ing product transportation. Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.

This manual is also suitable for:

Pci-7300a

Table of Contents