Ist Flag And Parallel Poll Enable Register (Ppe); Event Status Register (Esr) And Event Status Enable Register (Ese) - Rohde & Schwarz FSVA3000 User Manual

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R&S FSVA3000/ R&S
Bit No.
3
4
5
6
7
11.2.2.2

IST flag and parallel poll enable register (PPE)

As with the SRQ, the IST flag combines the entire status information in a single bit. It
can be read by means of a parallel poll or using the command *IST?.
The parallel poll enable register (PPE) determines which bits of the STB contribute to
the IST flag. The bits of the STB are "ANDed" with the corresponding bits of the PPE,
with bit 6 being used as well in contrast to the SRE. The IST flag results from the
"ORing" of all results. The PPE can be set using commands
mand *PRE?.
11.2.2.3

Event status register (ESR) and event status enable register (ESE)

The ESR is defined in IEEE 488.2. It can be compared with the EVENt part of a SCPI
register. The event status register can be read out using command *ESR?.
The ESE corresponds to the ENABle part of a SCPI register. If a bit is set in the ESE
and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STB is set.
The ESE register can be set using the command
*ESE?.
Table 11-3: Meaning of the bits used in the event status register
Bit No.
0
1
User Manual 1178.8520.02 ─ 08
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FSV3000
Meaning
QUEStionable status register summary bit
The bit is set if an EVENt bit is set in the QUEStionable status register and the associated
ENABle bit is set to 1. A set bit indicates a questionable instrument status, which can be speci-
fied in greater detail by querying the STATus:QUEStionable status register.
MAV bit (message available)
The bit is set if a message is available in the output queue which can be read. This bit can be
used to enable data to be automatically read from the instrument to the controller.
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set
and enabled in the event status enable register. Setting of this bit indicates a serious error which
can be specified in greater detail by polling the event status register.
MSS bit (main status summary bit)
The bit is set if the instrument triggers a service request. This is the case if one of the other bits
of this registers is set together with its mask bit in the service request enable register SRE.
STATus:OPERation status register summary bit
The bit is set if an EVENt bit is set in the OPERation status register and the associated
ENABle bit is set to 1. A set bit indicates that the instrument is just performing an action. The
type of action can be determined by querying the STATus:OPERation status register.
Meaning
Operation Complete
This bit is set on receipt of the command *OPC exactly when all previous commands have been
executed.
Not used
Network operation and remote control
Status reporting system
and read using com-
*PRE
and read using the command
*ESE
780