Xilinx Spartan-6 User Manual page 18
Fpga gtp transceiver signal integrity simulation kit
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Also See for Spartan-6:
- Design and pin planning manual (72 pages) ,
- User manual (40 pages) ,
- Getting started (37 pages)
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Appendix A: Frequently Asked Questions
2.
X-Ref Target - Figure A-2
18
What is the J0 symbol on the schematic screen
Figure A-2: J0 Symbol
The J0 symbol appears unconnected on the schematics screen and must not be
removed from the schematics. The J0 symbol inserts global simulation parameters,
such as .TEMP and .option compat (the HSPICE compatibility switch for Eldo) into
the project. These parameters are managed automatically by the configurator
programs. Removing J0 results in incorrect simulations.
www.xilinx.com
(Figure
A-2)?
Spartan-6 FPGA GTP Transceiver SIS Kit (HyperLynx)
UG396 (v1.0) June 10, 2010
UG396_c1_01_042010
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