Lpc Bus; I²C Bus; Sm Bus; Spi - Congatec COM Express conga-TCV2 User Manual

5.1.8

LPC Bus

The conga-TCV2 offers the LPC (Low Pin Count) bus through the AMD Embedded Ryzen V2000 SoC. For information about the decoded LPC
addresses, see section 9 "System Resources".
5.1.9 I²C Bus
The I²C bus is implemented through the congatec board controller and accessed through the congatec CGOS driver and API. The controller
provides a fast-mode multi-master I²C bus that has the maximum I²C bandwidth.
5.1.10

SM Bus

The SM bus is implemented through the congatec board controller and accessed through the congatec CGOS driver and API.
5.1.11

SPI

The SPI bus interface supports single and dual SPI interfaces with speeds up to 16 MHz. The conga-TCV2 discrete SPI TPM and the congatec
BIOS flash are connected on the SPI interface.
Note
The SPI bus is for external BIOS flash only.
5.1.12

GPIO

The conga-TCV2 offers General Purpose Input/Output signals on the A–B connector. The GPIO signals are controlled by the congatec Board
controller.
5.1.13

General Purpose Serial Interface

The conga-TCV2 offers two standard 16C550 UARTs on the A–B connector via the congatec Board Controller. The interfaces support up to
115200 baud rate.
Note
The UART interfaces do not support hardware handshake and flow control.
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