Analog Devices AD9779 Preliminary Technical Data page 16

AD9779
Register (hex) Bits
00 7
Comm Register
6
5
4
3
1
7:6
01
Digital Path Filter
Control
5:2
0
02 7
General Mode
Control
6
5
3
2
1
0
03 7:6
Data Clock Delay
5:3
2:0
7:4
04
Synchronization
3:0
Delay
05 7
Chip Sync and Data
Delay Control
6
5:3
Name Function
SDIO Bidirectional 0: Use SDIO pin as input data only
1: Use SDIO as both input and output data
LSB/MSB First 0: First bit of serial data is MSB of data byte
1: First bit of serial data is LSB of data byte
Software RESET Bit must be written with a 1, then 0 to soft reset SPI register map
Power Down 0: All circuitry is active
Mode
1: Disable all digital and analog circuitry, only SPI port is active
Auto Power Down
Enable
PLL LOCK (read 0: PLL is not locked
only)
1: PLL is locked
Filter Interpolation 00: 1x interpolation
Rate
01: 2x interpolation
10: 4x interpolation
11: 8x interpolation
Control Halfband See Table 13
Filters 1,2,3
Zero Stuffing 0: Zero stuffing off
1: Zero stuffing on
Data Format 0: Signed binary
1: Unsigned binary
One Port Mode 0: Both input data ports receive data
1: Data port 1 only receives data
Real Mode 0: Enable Q path for signal processing
1: Disable Q path data (clocks disabled)
Inverse Sinc 0: Inverse sinc disabled
Enable
1: Inverse sinc disabled
DATACLK Invert 0: Output DATACLK same phase as internal capture clock
1: Output DATACLK opposite phase as internal capture clock
IQ Select Invert 0: TxEnable (pin 39) =1, routes input data to I channel
TxEnable (pin 39) =0, routes input data to Q channel
1: TxEnable (pin 39) =1, routes input data to Q channel
TxEnable (pin 39) =0, routes input data to I channel
Q First 0: First byte of data is always I data at beginning of transmit
1: First byte of data is always Q data at beginning of transmit
Data Delay Mode 00: Manual, no error correction
01: Manual, continuous error correction
10: automatic, one pass check
11: automatic, continuous pass check
Data Clock Delay Data Clock delay control
Data Window Window delay control
Delay
Sync Output Delay
Sync Window
Delay
Sync Enable 0: LVDS and synchronization rceiver logic off
1: LVDS and synchronization rceiver logic on
Sync Driver Enable 0: LVDS driver off
1: LVDS driver on
DAC Clock Offset
Rev. PrD | Page 16 of 34
Preliminary Technical Data
for filter modes
Default
0
0
0
0
0
0
00
0000
0
0
0
0
0
0
0
00
000
000
0000
0000
0
0
0