Analog Devices AD9779 Preliminary Technical Data page 24

AD9779
Refe rence Clock
Refe rence Clock
Refe rence Clock
Using Data Delay to Meet Timing Requirements
In order to meet strict timing requirements at input data rates of up
to 250MSPS, the AD9779 has a fine timing feature. Fine timing
adjustments can be made by programming values into the DATA
CLOCK DELAY register (reg 03h, 5:3). By changing the values in
this register, delay can be added to the default delay between the
DACCLK in the DATACLK out. The effect of this is shown in
Figure 37 and Figure 38.
Figure 37. Delay from DACCLK to DATACLK out with CLK DATA DELAY = 000
tD
DATA CLK out
Input Data
Figure 34. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 2x Input Sample Rate
tD
DATA CLK out
Input Data
Figure 35. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 4x Input Sample Rate
tD
DATA CLK out
Input Data
Figure 36. Timing Specifications for AD9779, PLL Disabled, 4x Interpolation
tS
tS
tS
tS=-2.3ns typ
tH=3.7ns typ
tD=5.5ns typ
Figure 38. . Delay from DACCLK to DATACLK out with CLK DATA DELAY = 111
The difference between the default delay of Figure 37 and the
maximum delay shown in Figure 38 is the range programmable via
the DATA CLK DELAY register. The resulting delays when
programming DATA CLK DELAY between 000 and 111 are a
linear extrapolation between these two figures. (typically 300ps-
400ps per increment to DATA CLK DELAY).
Rev. PrD | Page 24 of 34
Preliminary Technical Data
tH
tH
tH