Table Of Contents - Analog Devices AD9779 Preliminary Technical Data

AD9779

TABLE OF CONTENTS

Specifications............................................................................................3
DC SPECIFICATIONS ......................................................................3
DIGITAL SPECIFICATIONS............................................................4
AC SPECIFICATIONS.......................................................................4
Pin Function Descriptions .....................................................................5
Pin Configuration....................................................................................6
Interpolation Filter Coefficients............................................................7
INTERPOLATION Filter RESPONSE CURVES................................8
CHARACTERIZATION DATA ............................................................9
General Description ..............................................................................12
Serial Peripheral Interface................................................................12
General Operation of the Serial Interface......................................12
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Updated Page 1 Features, added eval board schematics, SPI register map, filter coefficients and filter response curves
Revision PrC: Added characterization data, description of modulation modes, internal clock distribution architecture, timing information
Revision PrD: Added more ac characterization data, power dissipation
Instruction Byte .................................................................................12
Serial Interface Port Pin Descriptions ............................................12
MSB/LSB Transfers ...........................................................................13
Notes on Serial Port Operation .......................................................13
SPI Register Map ...............................................................................14
Internal Reference/Full Scale Current Generation.......................22
Auxiliary DACs..................................................................................22
Power Down and Sleep Modes........................................................22
Internal PLL Clock Multiplier / Clock Distribution.....................23
Timing Information ..........................................................................23
Interpolation Filter Architecture.....................................................25
EvaLuation Board Schematics..............................................................27
Rev. PrD | Page 2 of 34
Preliminary Technical Data