Analog Devices AD9779 Preliminary Technical Data page 17

Preliminary Technical Data
06 7
IRQ Status
6
5
3
2
1
07 7:3
PLL Band and Divide
2:0
08 7
PLL Enable and
Charge Pump
Control
6:5
4:3
2:0
09 7
Misc. Control
6
5:3
2:0
7:0
0A
IDAC Gain
0B 7
IDAC Gain and
Control
6
1:0
0C 7:0
Auxiliary DAC1 Gain
Data Delay Error
(read only)
Chip
Synchronization
Delay Error (read
only)
Cross Control
Error (read only)
Data Delay Error
Enable
Chip
Synchronization
Error Enable
Cross Control
Error Enable
PLL Band Select
Table 14
See for
values.
PLL Ripple Cap
Adjust
PLL Enable 0: PLL off, DAC rate clock supplied by outside source
1: PLL on, DAC rate clock synthesized internally from data rate clock via PLL
clock multiplier
PLL Output Divide 00: Divide by 1
Ratio
01: Divide by 2
10: Divide by 4
11: Divide by 8
PLL Loop 00: Divide by 1
Feedback Divide
01: Divide by 2
Ratio
10: Divide by 4
11: Divide by 8
PLL Loop Filter 000: PLL band select 00000-00111
Bandwidth Tuning
100: PLL band select 01000-01111
Recommended
110: PLL band select 10000-10111
Settings. See
111: PLL band select 11000-11111
Table 14
for PLL
Band Select
values.
PLL Error Bit 0: Phase error detect
Source
1: Range limit
PLL Reference 0: Use PLL reference
Bypass
1: Use DAC reference
VCO AGC Gain 000: PLL band select 00000-00111
Control. See Table
100: PLL band select 01000-01111
14 for PLL Band
110: PLL band select 10000-10111
Select values.
111: PLL band select 11000-11111
PLL Bias Current
Level/Trim
IDAC Gain (7:0) LSB slice of 10 bit gain setting word for IDAC
Adjustment
IDAC Sleep 0: IDAC on
1: IDAC off
IDAC Power Down 0: IDAC on
1: IDAC off
IDAC Gain (9:8) MSB slice of 10 bit gain setting word for IDAC
Adjustment
Aux DAC1 Gain (7:0) LSB slice of 10 bit gain setting word for Aux DAC1
Adjustment
Rev. PrD | Page 17 of 34
AD9779
0
0
0
0
0
0
11001
111
0
01
10
111
0
0
111
000
11111001
0
0
01
00000000