Digital Specifications; Ac Specifications - Analog Devices AD9779 Preliminary Technical Data

AD9779

DIGITAL SPECIFICATIONS

(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Differential peak-to-peak Voltage
DAC CLOCK INPUT
Common Mode Voltage
(CLK+, CLK-)
Maximum Clock Rate
Maximum Clock Rate (SCLK)
SERIAL PERIPHERAL
Maximum Pulse width high
INTERFACE
Maximum pulse width low

AC SPECIFICATIONS

(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter
Output Settling Time (tst) (to 0.025%)
Output Rise Time (10% to 90%)
DYNAMIC
PERFORMANCE
Output Fall Time (90% to 10%)
Output Noise (IoutFS=20mA)
f
DAC
SPURIOUS FREE
f
DAC
DYNAMIC RANGE
f
DAC
(SFDR)
f
DAC
f
DAC
TWO-TONE
f
DAC
INTERMODULATION
f
DAC
DISTORTION (IMD)
f
DAC
f
DAC
f
NOISE SPECTRAL
DAC
DENSITY (NSD)
f
DAC
f
DAC
WCDMA ADJACENT f
DAC
CHANNEL LEAKAGE
f
DAC
RATIO (ACLR), SINGLE
f
DAC
CARRIER
WCDMA SECOND f
DAC
ADJACENT CHANNEL
f
DAC
LEAKAGE RATIO
f
DAC
(ACLR), SINGLE
CARRIER
Parameter
= 100 MSPS, f = 20 MHz
OUT
= 200 MSPS, f = 50 MHz
OUT
= 400 MSPS, f = 70 MHz
OUT
= 800 MSPS, f = 70 MHz
OUT
= 200 MSPS, f = 50 MHz
OUT
= 400 MSPS, f = 60 MHz
OUT
= 400 MSPS, f = 80 MHz
OUT
= 800 MSPS, f = 100 MHz
OUT
= 156 MSPS, f = 60 MHz
OUT
= 200 MSPS, f = 80 MHz
OUT
= 312 MSPS, f = 100 MHz
OUT
= 400 MSPS, f = 100 MHz
OUT
= 245.76 MSPS, f = 20 MHz
OUT
= 491.52 MSPS, f = 100 MHz
OUT
= 491.52 MSPS, f = 200 MHz
OUT
= 245.76 MSPS, f = 60 MHz
OUT
= 491.52 MSPS, f = 100 MHz
OUT
= 491.52 MSPS, f = 200 MHz
OUT
Temp Test Level
Table 2: Digital Specifications
Temp Test Level
Table 3: AC Specifications
Rev. PrD | Page 4 of 34
Preliminary Technical Data
Min Typ Max
800
400
1
40
TBD
TBD
Min Typ Max
TBD
TBD
TBD
TBD
82
82
84
87
91
88
81
88
-158
-157
-159
-159
80
79
74
78
80
76
Unit
mV
mV
GSPS
MHz
ns
ns
Unit
ns
ns
ns
pA/rtHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
dBc
dBc
dBc