Headers; Expansion Interface; Table 6-5. Header Assignments; Table 6-6. Expansion Interface - Cirrus Logic ARM CDB89712 User Manual

6.3.4

Headers

Table 6-5 describes the headers for the CS89712 Development Board.
Location
JP21
JP24
JP34
JP19, JP20,
JP22, JP23
JP15
JP31
JP27-30
J4-7
6.3.5

Expansion Interface

This expansion interface is intended to support the addition of small add-on boards. The interface
exposes sufficient signals to allow byte-wide interfacing to peripheral devices. It should be noted
that the interface is 3.3V only.
For a detailed explanation of this interface refer to the CS89712 Data Sheet.
Description
D0
D1
D2
D3
D4
D5
D6
D7
nCS5 (Chip Select)
nMOE (Output Enable)
6-4
Name
MULTI-ICE
MULTI-ICE
TTL SERIAL PORT 1
Expansion headers for
user defined options
RS232 EN-DIS
TTL/SER2
CPU CONFIG
PROCESSOR PINS

Table 6-5. Header Assignments

Pin No.
1
3
5
7
9
11
13
15
17
19

Table 6-6. Expansion Interface

Description
Connection to Multi-ICE or Wiggler
Connection to Multi-ICE.
TTL connection to Serial Port 1
Refer to schematic for details on header pin assignments.
Enable / disable Serial Port 1
TTL I/O for Serial Port 1
Configures CPU clock speed and boot operation.
Intended for future product development. In future, this
board may be manufactured with the processor depopu-
lated and a separate processor carrier board dropped onto
these sites.
Pin No.
2 V
4 A0
6 A1
8 A2
10 A3
12 nMWE (Write Enable)
14 nEXTFIQ (Interrupt)
16 PD1 (GPIO)
18 GND
20 GND
CDB89712
Description
(3.3V)
DD
DS502UM2