Functional Block Diagram; Memory; Sdram; Figure 3-1. Cs89712 Functional Block Diagram - Cirrus Logic ARM CDB89712 User Manual

3.3 FUNCTIONAL BLOCK DIAGRAM

3.6864 MHZ
32.768 KHZ
NPOR, RUN,
RESET, WAKEUP
BATOK, EXPWR
PWRFL, BATCHG
EINT[1-3], FIQ,
MEDCHG
FLASHING LED DRIVE
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0–7)
BUZZER DRIVE
DC-TO-DC
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
ADCCS
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
SSIRSFR

3.4 MEMORY

There are two types of external memory present on the development board:
l
16MB SDRAM
l
8MB FLASH
3.4.1

SDRAM

The SDRAM provided is sufficiently large to meet the needs of all potential applications and
provides a fast access data area.
The 16 MByte SDRAM memory is provided as a single 32-bit bank, made up from two 1,048,576
X 16 X 4 (word X bit X bank) 64Mbit memories.
When the board is initialized from Ice_boot in the Flash memory, the SDRAM is mapped to
0x0000:0000 to 0x007F:FFFF. This SDRAM area is used for code/data storage, and also contains
the LCD buffer data.
It may be desirable to rearrange the SDRAM. This can be accomplished by programming the MMU.
A detailed discussion of setting up the MMU is beyond the scope of this manual, and the reader is
directed to the ARM Architectural Reference Manual for further information.
3-2
10BASE-T
ETHERNET
PLL
ARM720T
32.768 KHZ
-
OSCILLATOR ARM7TD
STATE CONTROL
8-KBYTE
CACHE
POWER
MANAGEMENT
MMU
INTERRUPT
CONTROLLER WRITE
BUFFER
RTC
GPIO TIMER
PWM
ON-CHIP
SSI1 (ADC)
BOOT ROM
DAI
EPB
SSI2
EPB BUS
CODE

Figure 3-1. CS89712 Functional Block Diagram

INTERNAL DATA BUS
D[0-31]
MEMORY CONTROLLER
EXPCLK, WORD,
EXPANSION
NCS[0:3], EXPRDY,
CONTROL
WRITE
MOE, MWE, SDCLK,
SDRAM CNTRL
SDQM[0:1], SDRAS,
SDCAS
INTERNAL ADDRESS BUS
A[0-27],
DRA[0-14]
LCD
TEST AND
ICE-JTAG
DEVELOPMENT
LCD
LCD DRIVE
CONTROLLER
ON-CHIP SRAM
LED AND
48K BYTES
IrDA
PHOTODIODE
ASYNC
UART
INTERFACE 1
ASYNC
UART
INTERFACE
CDB89712
2
DS502UM2