Flash Memory Interface Settings (Jp15-18); Momentary Switches; Table 4-2. Flash Memory Interface Settings; Table 4-3. Description Of Momentary Switches - Cirrus Logic ARM CDB89712 User Manual

4.4.2

Flash Memory Interface Settings (JP15-18)

The interface to the Flash memory is controlled by jumpers JP15, 16, 17 and 18. The settings are
shown in table Table
Jumper
JP15 16 / 32 BIT
FLASH ENABLE
JP16, SELECT 16 / 32
JP17, BIT FLASH
JP18
4.4.3

Momentary Switches

The switches listed in
the development board.
Switch Label
WAKEUP
RESET
POR
S2
4-6
4-2.
Name
16 bit Flash memory enabled. disables the
most significant word of the Flash memory
(U7).
32 bit Flash memory enabled. Enables the
most significant word of the memory (U7).
(Factory setting)
16 bit selected. This adjusts the addressing
of the Flash memory to short word (16 bit)
JPn
addressing, so that A1 is the LSB of the
address going to the Flash memory. This
setting is only valid when JP15 is not
installed.
32 bit selected. This setting aligns the Flash
memory address to long word (32 bit)
JPn
boundaries, so that the LSB of the address
to the Flash memory is A2. This setting is
only valid when JP15 is installed. (Factory
setting)

Table 4-2. Flash Memory Interface Settings

Table 4-3 are switches that are held down momentarily to initiate an action on
CS89712 Signal
WAKEUP Forces CS89712 into Operating state
nURESET Resets CS89712, CS8900A, PS6700, and JTAG/ICE.
nPOR Power on reset. This switch can override any processor state,
and will reset the real-time-clock.
Factory test only.

Table 4-3. Description of Momentary Switches

Description
Switch Description
CDB89712
DS502UM2