Npwfrl; Waking Up The Board; Development Board Interfaces; Serial Ports - Cirrus Logic ARM CDB89712 User Manual

3.8.1.3. nPWFRL

Power failure; when active, this signal will generate an internal reset and place the CS89712 into
Standby State. This signal is generated from a switch labelled PWRFL on the CDB89712.
3.8.2

Waking up the Board

Once the CS89712 has been reset, it enters Standby. The transition from the Standby state to the
Operating state is triggered by a rising edge on the Wakeup pin. Control of the Wakeup pin is
implemented with a momentary switch labelled WAKEUP located at the front of the development
board. For more information on resetting and waking up the ARM processor, see Application Note
AN186, "Bringing Up the EP72/73XX Device", which is available on the Web site.

3.9 DEVELOPMENT BOARD INTERFACES

3.9.1

Serial Ports

There are two serial ports on the board, numbered 0 and 1. Serial Port 0 is always in its powered up
state. Port 0 can be disabled, but not powered down, by installing a jumper on JP36, which holds the
Data Terminal Ready (DTR) line low. If the jumper is removed, the DTR line is held high. Serial
Port 1 is disabled by installing a jumper on JP35.
3.9.2

Ethernet Port

The CDB89712 has one 10BASE-T Ethernet port, J3. It is connected to the Ethernet pins on the
CS89712 through a set of transformers in U11.
3.9.3

JTAG Connectors for ICE

The two JTAG connectors allow a 14 pin or 20 pin cable to be connected as an In Circuit Emulator.
3.9.4

IrDA Port

U14 is an IrDA transceiver that connects directly to the IrDA port on the CS89712.
3.9.5

Expansion Headers

The I/O pins of the CS89712 are brought out to headers for connecting a display, keyboard, Digital
Audio Interface (DAI) and other I/O devices. These devices were not included on the CDB89712 so
that the board could be customized by the user through the expansion headers.
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CDB89712
DS502UM2