Quectel EM06 Series Manual page 37

The following table shows the pin definition of PCM and I2C interfaces which can be applied to audio
codec design.
Table 11: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No.
PCM_IN 22
PCM_OUT 24
PCM_SYNC 28
PCM_CLK 20
I2C_SCL 58
I2C_SDA 56
The clock and mode can be configured by AT command, and the default configuration is the master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [2] for details about AT+QDAI command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_CLK
PCM_SYNC
PCM_OUT
Module
Figure 21: Reference Design of PCM Application with Audio Codec
EM06_Series_Hardware_Design
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO
synchronization signal
IO PCM data bit clock
DO I2C serial clock
IO I2C serial data
PCM_IN
I2C_SCL
I2C_SDA
1.8 V
EM06 Series Hardware Design
Comment
1.8 V power domain.
1.8 V power domain.
1.8 V power domain.
1.8 V power domain.
In the master mode, it serves as
an output signal.
In the slave mode, it serves as
an input signal.
If unused, keep it open.
Used for external codec.
Need to be pulled up to 1.8 V.
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
LTE-A Module Series
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