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Instructions that directly alter addressed registers could affect the other status flags if the
instruction is applied to the PSW. Status flags can also be modified by bit manipulation.
4.3.2
Instruction Table
Table 4-3
lists all the instructions supported by XC800. Instructions are 1, 2 or 3 bytes
long as indicated in the 'Bytes' column. Each instruction takes 1, 2 or 4 machine cycles
to execute (with no wait state). One machine cycle comprises 2 CCLK clock cycles.
Table 4-3
Instruction Table
Mnemonic
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
User's Manual, V 0.1
Description
ARITHMETIC
Add register to A
Add direct byte to A
Add indirect memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect memory to A with
carry
Add immediate to A with carry
Subtract register from A with
borrow
Subtract direct byte from A with
borrow
Subtract indirect memory from A
with borrow
Subtract immediate from A with
borrow
Increment A
Increment register
Increment direct byte
Increment indirect memory
Decrement A
Decrement register
Decrement direct byte
Decrement indirect memory
Hex Code Bytes
28-2F
26-27
38-3F
36-37
98-9F
96-97
08-0F
06-07
18-1F
16-17
4-6
XC800
Instruction Set
Cycles
1
25
2
1
24
2
1
35
2
1
34
2
1
95
2
1
94
2
04
1
1
05
2
1
14
1
1
15
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2005-01
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